Spiking Neural Networks (SNNs) are bio-plausible models that hold great
potential for realizing energy-efficient implementations of sequential tasks on
resource-constrained edge devices. However, commercial edge platforms based on
standard GPUs are not optimized to deploy SNNs, resulting in high energy and
latency. While analog In-Memory Computing (IMC) platforms can serve as
energy-efficient inference engines, they are accursed by the immense energy,
latency, and area requirements of high-precision ADCs (HP-ADC), overshadowing
the benefits of in-memory computations. We propose a hardware/software
co-design methodology to deploy SNNs into an ADC-Less IMC architecture using
sense-amplifiers as 1-bit ADCs replacing conventional HP-ADCs and alleviating
the above issues. Our proposed framework incurs minimal accuracy degradation by
performing hardware-aware training and is able to scale beyond simple image
classification tasks to more complex sequential regression tasks. Experiments
on complex tasks of optical flow estimation and gesture recognition show that
progressively increasing the hardware awareness during SNN training allows the
model to adapt and learn the errors due to the non-idealities associated with
ADC-Less IMC. Also, the proposed ADC-Less IMC offers significant energy and
latency improvements, 2β7Γ and 8.9β24.6Γ, respectively, depending
on the SNN model and the workload, compared to HP-ADC IMC.Comment: 12 pages, 13 figure