In this work, an asymmetrical bulk-linearized composite MOSFET is presented, with an enhanced linear range and an equivalent saturation voltage of up to several hundred mV
even in weak inversion, allowing to implement large MOS resistors. Some preliminary measurements are presented, as well as 150MΩ and 200MΩ equivalent resistors simulations, with a linear range up to 1.5V. A low frequency, 40dB gain, fully integrated cardiac sensing channel filter/amplifier is also shown. Taking advantage of the proposed technique, the circuit consumes only 25nA of supply current.Agencia Nacional de Investigación e Innovació

Arnaud Maceira, Alfredo

Chacón Rodríguez, Alfonso

Gak Szollosy, Joel

Miguez de Mori, Matías Rafael

Puyol, Rafael

English

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Abstract—In this work, an asymmetrical bulk-linearized composite MOSFET is presented, with an enhanced linear range and an equivalent saturation voltage of up to several hundred mV even in weak inversion, allowing to implement large MOS resistors. Some preliminary measurements are presented, as well as 150MΩ and 200MΩ equivalent resistors simulations, with a linear range up to 1.5V. A low frequency, 40dB gain, fully integrated cardiac sensing channel filter/amplifier is also shown. Taking advantage of the proposed technique, the circuit consumes only 25nA of  supply current. Index Terms— analog integrated circuits, CMOS, linearization techniques, analog filters, MOS resistor. I. INTRODUCTIONULK degeneration completes the three basic techniques used for linearization of the MOS transistor, the two other are source and gate degeneration [1,2,3]. Yet, bulk linearization of a MOS differential pair was only introduced in 2007 [4] (and further developed in [5,6]) where an increasing compensating voltage is applied to the bulks of a differential pair, thus decreasing the transconductance and increasing the linear range. The technique is proposed in [4] including simulations, a measured transconductor and a nano-power Gm-C filter are presented in [5], while a high frequency OTA is presented in [6] including measurements of the HD3 distortion optimumalready simulated in [4,5]. A similar concept was introduced fora single MOSFET operating in the triode region in [7], applyinga compensating voltage to the bulk in order to widen the linearregion. The idea is retaken in this work: firstly, a newasymmetrical bulk-modified transistor is presented, and novelcircuits are proposed to implement practical MOS pseudo-resistors based in this structure up to hundreds MΩ. Finally, aG = 200, 1.5VPP output bandpass amplifier for cardiac activitydetection in pacemakers is presented, which consumes only 25nA thanks to the use of bulk-linearized pseudo-resistors.II. AN ASYMMETRICAL BULK-MODIFIED MOS COMPOSITETRANSISTOR WITH ENHANCED LINEARITY In the so-called MOS resistor, the transistor is operated at the beginning of the triode region, where the drain-source voltage A. Arnaud, R. Puyol, M.Miguez, J.Gak, are with Universidad Católica delUruguay, Av.8 de Octubre 2738, Montevideo, CP11600, Uruguay (e-mail: aarnaud@ucu.edu.uy). 978-1-7281-0453-9/19/$31.00 ©2019 IEEEVDS is small, with fixed bulk and gate voltages. The drain current ID should be proportional to VDS but, due to the non-linear nature of the MOS itself, the linear range is severely limited as in Fig. 1a. The basic idea of using the bulk to  extend the linear region is shown in Fig. 1b, where the bulk is connected to the drain of M1 (VGS is fixed). The slope (rMOS)-1 of ID(VDS) can be calculated with a small signal analysis:  𝑖 = (𝑔 + 𝑔 ) ∙ 𝑣     ⇒ 𝑟 = (𝑔 + 𝑔 ) (1) where gmb, gmd, are the bulk and drain transconductances respectively. The MOS equivalent resistance rMOS is not constant because both gmb, gmd, depend on VDS. At VDS = 0V, gmb = 0, and the drain transconductance is a given value gmd = gmdo; when VDS increases, gmd decreases, becoming virtually 0 as M1 saturates, but gmb increases thus the bulk modulates ID. For a MOS behaving as a resistor, rMOS(VDS) in (1) should be constant (gmb increase should compensate gmd decay). While for the large signal MOS it is not straightforward to develop an analytic expression of (1), the design space can be explored with a SPICE simulator; the result for a long transistor with W1/L1 = 1µm/10µm is shown in Fig.1b (VGS ≈ VT) with a quasi-linear range up to 400mV when the bulk-source diode starts conducting a significant current. In effect, the problem with the circuit in Fig. 1b is the directly biased diode triggering the drain current, and eventually latchup as VDS increases. To overcome this problem and to further enhance the linear range, the proposed bulk-modified composite transistor is shown at the top of Fig.2: M1 has been split in two series transistors, M1a sized (W/L)1a, and M1b sized (W/L)1b, and the bulk voltage VB is generated from the M1a-M1b MOS divider itself. A reference current and a diode-connected transistor MBias = M1b are used to set VG. Moreover, M1a-M1b can be considered as an equivalent 3-terminal composite MOS Meq that saturates for a large VSat_eq > 400mV as depicted in Fig.2. The linear region is greatlyextended, the best linearity results were obtained for (W/L)1a >>(W/L)1b thus the composite transistor will be asymmetrical.When VDS increases, as (W/L)1a >> (W/L)1b, the voltage drop inM1a is small so M1b rapidly saturates, while M1a remains in theA. Chacón-Rodríguez is with Tecnológico de Costa Rica, Cartago. This Project was partially funded by ANII-Uruguay, under grant FMV_1_2017_1_136543. An asymmetrical bulk-modified composite MOS transistor with enhanced linearity Alfredo Arnaud, Senior Member, Rafael Puyol, Member, IEEE, Alfonso Chacón-Rodríguez, Senior Member, IEEE, Matías Miguez, Member, IEEE, Joel Gak, Member, IEEE. B2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)49Authorized licensed use limited to: ANII. Downloaded on October 19,2021 at 19:32:02 UTC from IEEE Xplore.  Restrictions apply. linear region.  But as M1a source VS1a (connected to VB) increases, VGS1a  decreases to such an extent that, at certain point, ID is close to the saturation current of M1a. From this point on, the voltage drop in M1a increases rapidly, and Meq transistor reaches saturation resembling a cascode. The simulations in Fig. 1, 2, 4, 5, correspond to a 0.6µm technology with VTN  1V; in Fig.2 (W/L)1a = 10µm/1µm, (W/L)1b = (W/L)Bias =  1µm/40µm. Preliminary measurements for bulk-linearized MOSFETs using ALD1106 quad discrete transistors in the configuration of Fig.2 are shown in Fig. 3. M1a, and M1b of Fig. 2 were implemented with 4-parallel and 4(8)-series transistors respectively. The measured linearization effect is remarkable, but quite limited in comparison to Fig. 2 because of the limited aspect ratio of these discrete MOSFETs. Notice that the Meq composite transistor can be effectively considered as a single unit transistor. In Fig. 4 several ID(VDS) curves, the equivalent saturation current ISat(VGS), and the equivalent [gm/ID] ratio, are shown for a composite Meq (continuous line) and a single reference transistor MRef (dash-dot line). Meq can be utilized to implement operative current mirrors and differential pairs, but are of little practical interest because of the large VSat_eq. On the other hand, Meq can be exploited to efficiently implement MOS pseudo resistors with enhanced linearity in a reduced die area.  III. HIGH VALUE RESISTORS USING COMPOSITE TRANSISTORSVery large pseudo-resistors using MOSFETs can beimplemented therefore by stacking successive stages like the one in Fig. 2. Firstly, three blocks are connected in series as shown in Fig. 5 to implement a resistor close to RMOS ≈ 200MΩ with a quasi-linear range of almost 1V. The transistors are sized (W/L)a = 10m/0.6m, (W/L)b = (W/L)Bias = 0.6m/60m; the 0.6nA and 1nA bias currents are implemented with PMOS current mirrors (not shown) and were adjusted to fine tune the Fig. 4. Simulated ID(VDS) for different VGS values (top plot), saturation current ISat and gm/ID ratio (bottom plot); for a bulk-modified composite transistor (continuous line) Wa/La = 10m/0.6m, Wb/Lb = 0.6m/10m, and a standard NMOS (dash-dot line) MRef = 0.6m/10m. 00.20.40.60.810 0.2 0.4 0.6 0.8 1I D[µA]VDS [V]VGS = 1.5V VGS = 1.4VVGS = 1.3VVGS = 1.2VVGS = 1.1VVGS = 1.0VVGS = 0.9VVGS = 1.5VVGS = 1.4VVGS = 1.3VVGS = 1.2VVGS = 1.1V38131823280.0010.010.111010010000.4 0.6 0.8 1 1.2 1.4CompositeSingle MOSI Sat[nA]g m/ID[V-1]ISat & gm/IDFig. 1.  a) Simulated ID(VDS) for a standard NMOS; b) a very basic bulk linearized MOS; W/L = 1µm/10µm, VGS close to threshold voltage VT. Fig. 2. The proposed asymmetrical bulk-modified MOS. Meq on top, and  simulated ID(VDS) transfer (straight lines) for typical, worst-slow, worst-powerfoundry models (TM, WP, WS). Two reference transistors (dash-dot lines) are included to compare the impact of linearization. Note the equivalent VSat_eqabove 400mV. Fig. 3 Measured bulk-linearized MOS using discrete transistors. MBias 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)50Authorized licensed use limited to: ANII. Downloaded on October 19,2021 at 19:32:02 UTC from IEEE Xplore.  Restrictions apply. linearity. The addition of the bias currents in Fig. 5 makes the equivalent drain and source currents to be different: IA  IB, and thus shifts the IA(VAB) curve (to restore IA = IB, properly matched sink currents can be added at VG1,G2,G3 gate nodes). Using this circuit to emulate a resistor has, nonetheless, the major drawback of requiring VAB > 0, which seriously limits the range of possible applications. A solution is given in Fig. 6 where two blocks Mup and Mlow like the one in Fig. 2, are connected in series in opposite direction and sharing the gate ((W/L)a = (W/L)c, (W/L)b = (W/L)d = (W/L)Bias. Since VGS for the lower composite transistor Mlow is higher, it practically does not affect ID. The circuit is symmetrical thus the ID(VDS) is so, as depicted in the plot of Fig.6 corresponding to preliminary measurements using ALD1106 quad discrete transistors. Just as in Fig.3, the measured linearization effect is quite limited due to the aspect ratio of the discrete MOSFETs. But the results are amazing in Fig.7 where very different aspect ratios for the transistors were simulated, for two blocks analogous to the one in Fig. 6 connected in series, using PMOS transistors in a 0.18µm CMOS technology. A 150MΩ resistor is shown, with approximately 1.5V linear range, and consuming only 2nA current to bias the gates; the combined effect of the opposite stacked blocks also helps to compensate slight rMOS(VDS) variations in (1) that can be observed in Fig.2 for a VDS small (before M1b saturates). In Fig.7 sink bias currents are used to set M1i gate voltage, and matched source currents are included for the sake of symmetry (to make IA = IB again). The linear range to current consumption trade-off, is better than any other reported small transconductance OTA (see [5] for a survey). IV. A 40 NA CARDIAC SENSE CHANNEL FOR IMPLANTABLEPACEMAKERS USING BULK-LINEARIZED MOS RESISTORS A practical utilization of the linearized 147MΩ MOS resistor in Fig.7 is shown in Fig. 8, where a nano-power filter-amplifier for biomedical applications is presented. On the right side of the picture the Gm-R-C filter is shown while transistor-level schematics for Gm1-Gm1’ OTA are shown on the left. The idea was to substitute the very low transconductance linear OTAs that consume current in a Gm-C filter [5], by MOS resistors. In the proposed filter Gm1-Gm1’ form a dual differential input transconductor with Gm1 =125nS, Gm1’ =38nS. The transconductor Gm2 is utilized as an operational amplifier implementing an ideal integrator with C2. Assuming a virtual VRef at the positive input of Gm2, Gm1-R1-C1 form a low-pass gain stage, and R1-Gm2-C2 act as an integrator:   𝑉 = ∫ 𝑉 (𝑡) (𝐶 ∙ 𝑅 )⁄ ∙ 𝑑𝑡        (2) Thus, it acts as a DC cancellation loop. In the filter C1 = 5pF, Fig. 5. Three stacked bulk-linearized MOS form a 200MΩ equivalent resistor; Wa/La = 10m/0.4m, Wb/Lb = 0.6m/40m, simulated results on the left. Fig. 6. Proposed circuit block to implement direct-reverse MOS resistors, and measured results using discrete transistors. For the plot, M1a,c and M1b,d, were implemented with 4-parallel and 4-series unitary transistors respectively (each unitary transistor is ¼ ALD1106). Fig. 7. Two double-sided linearized PMOS forming a ≈150MΩ equivalent resistor; Wa,c/La,c = 10m/0.4m, Wb,d/Lb,d = 0.6m/40m. Simulated results on the bottom. 1 nA1 nA1 nA1 nABAM1bM1aM1cM1dM2BA-6-4-20246-1.5 -1 -0.5 0 0.5 1 1.5Resistor Current IABVAB [V]I AB[nA]Slope = (147 MΩ)-12019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)51Authorized licensed use limited to: ANII. Downloaded on October 19,2021 at 19:32:02 UTC from IEEE Xplore.  Restrictions apply.     C2 = 4pF, and Gm2 ≈ 1nS is a symmetrical OTA with a 2nA bias current, and 32:1 series-parallel current division to the output as proposed in [8] to achieve a very low transconductance. The filter of Fig.8 is intended to amplify cardiac signals in an implantable pacemaker for natural heart beat detection. Cardiac sensing is a well-known application [9, 10]; the objective is to amplify 100µV – 10mV input signals and bandpass filter them around 70Hz-200Hz. A detailed description of the complete cardiac sensing signal processing chain (amplifier-filter + comparator, offset compensation, etc.) is omitted in this work for the sake of simplicity. For the minimum signal, the gain of the filter in Fig.9 is not enough, and thus two series stages need be employed with a total gain GTot = 49dB, and 40db/dec decay to eliminate noise out of the band of interest. For larger cardiac signals, it is easy to reduce the gain altering the R1 biasing in Fig.7. In Fig.9, and Fig. 10, the simulated transfer function of the 2-stage filter, and the simulated output total harmonic distortion (THD) are shown. The circuit was simulated for VDD in the range from 1.8V to 3.3 V in a 0.18µm technology and consumes only 25nA in supply current. The THD is adequate for biomedical applications and is mostly the result of the 2nd harmonic effect. V. CONCLUSIONS In this work a bulk-linearization technique was presented, to enhance the linearity of the MOS transistor behaving as a resistor, using two series MOSFETs with the bulk connected to the midpoint. If properly designed, the resulting composite structure is linear up to an equivalent saturation voltage of several hundred mV. This asymmetrical bulk-modified composite MOS can be considered as a new transistor, with slightly degraded characteristics but enhanced linearity. Simulations and preliminary measurements using discrete transistors were presented. A 200MΩ 1V-linear equivalent resistor, and a 150MΩ 1.5V linear resistor were simulated stacking series linearized MOSFETs. For the latter, a technique was developed that allows to connect the equivalent resistor in both senses of the current flow. Finally, a biomedical circuit application example featuring a 25nA supply current, 49dB gain, 40dB/dec filter for cardiac signal detection was presented, using this technique to reduce the power consumption to a minimum in comparison to previously reported equivalent blocks. The proposed amplifier can substitute pure Gm-C, continuous time, or SC filter stages in [5, 9, 10] with a remarkable reduction of both supply current and supply voltage. REFERENCES  [1] F. Krummenacher and N. Joehl, "A 4-Mhz CMOS continuous-time filter with on-chip automatic tuning, " IEEE J. Solid State Circuits, vol. 23, no. 3, pp. 750–758, June 1988. [2] R. Sarpeshkar, R. F. Lyon, C. Mead, "A Low-Power Wide-Linear-Range Transconductance Amplifier," J. of Analog Integr. Circuits and Signal Process., vol. 13, pp. 123-151, May 1997. [3] A. Sheikholeslami, "Source Degeneration [Circuit Intuitions]," IEEE Solid-State Circuits Mag., vol.6, no.3, pp.5-6, 2014, DOI.10.1109/MSSC.2014.2329233 [4] P. Monsurrò, S. Pennisi, G. Scotti, A. Trifiletti, "Linearization Technique for Source-Degenerated CMOS Differential Transconductors," IEEE Trans. Circuits and Systems II, vol.54, no.10, pp.848–852, Oct.2007. [5] J. Gak, M.R. Miguez, A. Arnaud, “Nanopower OTAs With Improved Linearity and Low Input Offset Using Bulk Degeneration”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol.61, no.3, pp.689–698, Sept.2014, DOI. 10.1109/TCSI.2013.2284002. [6] G. Thomas-Erviti, et al.: “CMOS transconductor with improved linearity using the bulk of self-cascode transistors”, Electron. Lett., vol.53, no.3, pp.136-138, Feb.2017, DOI.10.1049/el.2016.4107. [7] A. Arnaud and M.R. Miguez, "Bulk linearisation of the MOS resistor," in Electron. Lett., vol.54, no.19, pp. 1106-1108, Sept.2018, DOI.10.1049/el.2018.5482 [8] A. Arnaud, R. Fiorelli, C. Galup-Montoro, “Nanowatt, sub-nS OTAs, with sub-10-mV input offset, using series-parallel current mirrors”, IEEE J. Solid State Circuits, vol.41, no.9, pp. 2009-2018, may 2010. [9] L. Lentola, A. Mozzi, A. Neviani, and A. Baschirotto, “A 1 µA front end for pacemaker atrial sensing channels with early sensing capability” IEEE Trans. on Circuits and Syst. II: Analog & Digital Signal Proc., vol.50, no. 8, pp. 397–403, Aug.2003. DOI: 10.1109/TCSII.2003.813591 [10] F.Silveira, D.Flandre, “A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator” in Procs. IEEE International Symposium on Circuits and Systems, ISCAS’2002, vol.5, may.2002, DOI: 10.1109/ISCAS.2002.1010670  Fig. 8. The proposed Gm-R-C filter-amplifier .  Fig. 9. Simulated AC transfer function of a two stage, 40 dB/dec, filter for cardiac sensing.   Fig. 9. Simulated output THD@130Hz of the filter   2025303540455010 100 1000Gain vs. freqGain[dB]Freq.[Hz]-45-40-35-30-25-2010 100 1000THD vs. OutputVOut [mV]THD [dB]2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)52Authorized licensed use limited to: ANII. Downloaded on October 19,2021 at 19:32:02 UTC from IEEE Xplore.  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An asymmetrical bulk-modified composite MOS transistor with enhanced linearity

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An asymmetrical bulk-modified composite MOS transistor with enhanced linearity

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