PostprintThis work presents an approach for accurate MOS transistor matching calculation. Our model, which is based on an accurate physics-based MOSFET model, allows the assessment of mismatch from process parameters and valid for any operating region. Experimental results taken on a test set of transistors implemented in a 1.2 /spl mu/m CMOS technology corroborate the theoretical development of this work

Arnaud, Alfredo

Galup Montoro, Carlos

Klimach, H

Schneider, M. C

English

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CONSISTENT MODEL FOR DRAIN CURRENT MISMATCH IN MOSFETS USING THE CARRIER NUMBER FLUCTUATION THEORY  H. Klimach1,2, A. Arnaud3, M. C. Schneider1, and C. Galup-Montoro1  1 Universidade Federal de Santa Catarina, Brazil, 2 Universidade Federal do Rio Grande do Sul, Brazil,  3 Universidad de la Republica, Uruguay  ABSTRACT  This paper presents a new approach for accurate MOS transistor matching calculation. Our model, which is based on an accurate physics-based MOSFET model, allows the assessment of mismatch from process parameters and is valid for any operating region. Experimental results taken on a test set of transistors implemented in a 1.2 µm CMOS technology corroborate the theoretical development of this work.  Index Terms – MOSFET, analog design, matching, compact models.  1. INTRODUCTION  It is widely recognized that the performance of most analog or even digital circuits is limited by MOS transistor matching [1-4]. The shrinkage of the dimensions of MOSFETs and the reduction in the supply voltage make matching limitations even more important to such an extent that several new studies have been published in recent years [5-8]. Existing mismatch models use either simple drain current models limited to a specific operating region [1, 2, 4, 7, 8] or complex expressions [6] like that of BSIM. In general, however, the applicability of dc current models to characterize mismatch is not questioned. It is widely accepted that matching can be modeled by the random variations in geometric, process and/or device parameters. The effect of the random parameters on the drain current is quantified using the dc model of the transistor. As pointed out in [7, 8] there is a fundamental flaw in this approach that results in inconsistent modeling of matching. In effect, mismatch models implicitly assume that the actual values of the lumped model parameters can be obtained integrating the position-dependent distributed models over the areas of the channel region of the device, e.g., for the threshold voltage VT  ∫∫−=areachannelTT dxdyyxVWLV ),(1   (1) where W and L are the width and the length of the transistor, respectively.  As analyzed in [7, 8], the application of (1) to series or parallel association of transistors leads to an inconsistent model of matching owing to the nonlinear nature of MOSFETs. Consequently, the simple consideration of random fluctuations in the lumped parameters of the dc current model is not appropriate to develop matching models and new formulas must be derived from basic principles. Fortunately, the formalism needed to model matching is already available in low frequency (LF) noise modeling. In this paper, we will show that the carrier number fluctuation theory [9], employed to derive LF transistor noise, can be adapted to model current matching in MOSFETs. To obtain general results for all bias regions of the transistor we have used the Advanced Compact MOSFET (ACM) model, a physics-based one-equation all-region model [10].   2. THE ACM MODEL  According to ACM [10], the drain current in a long-channel transistor is given by,  ( )dxdQnCQnCWI ItoxIoxD''''φµ +−=   (2) where Q’I  is the inversion charge density, n is the slope factor, C’ox is the oxide capacitance per unit area, µ is the effective mobility and φt is the thermal voltage. The other specificity of the ACM model is the use of the unified charge control model (UCCM) [12] to link the carrier charge density with the applied voltages +−=−''''ln1IPIIPItXPQQQQVV φ   (3) where Q’IP = −nC’oxφt , VP = (VGB−VT)/n is the pinch-off voltage, and VX is the channel potential. As shown in [13] the use of (2) in conjunction with (UCCM) (3) gives  XID dVQdxWI 'µ−=  .   (4) Consequently, the ACM model is fully consistent with the quasi-Fermi potential formulation for the drain current [11].  3. CONSISTENT SMALL-SIGNAL MODEL OF THE MOSFET CHANNEL  To calculate the effect of the fluctuations on the drain current along the channel, we split the transistor into 3 series elements: the upper transistor, the lower transistor, and a small channel element of length ∆x and area ∆A=W∆x (Fig. 1(a)). Small-signal analysis allows one to calculate the effect of the local current fluctuation (i∆A) on the drain current (∆Id), as shown in Fig. 1(b). The current division between the channel element and the equivalent small-signal resistance of the rest of the channel gives ∆Id = (∆x/L)i∆A. This very simple result for the current division, proportional to a geometric ratio, is a consequence of the quasi-Fermi potential formulation for the drain current, i.e., the conductance of the channel element and the transconductances of the upper and lower transistors are proportional to the local charge density. Thus, the square of the total drain current fluctuation is ( ) ( )[ ] ( )[ ]∫∑∑ ∆∆→∆∆=∆=∆=∆LAAxLdD dxixLiLxII0222022 1lim)( . (5)              Fig. 1. Splitting of a transistor into three series elements (a) Transistor equivalent circuit (b) Small-signal equivalent circuit   4. NUMBER FLUCTUATION MISMATCH MODEL  The relationship between local fluctuation of the inversion charge density and the local current fluctuation that follows from expression (4) is ''IIDAQQIi∆=∆      (6) where ∆Q’I  is the fluctuation of the inversion charge density in the channel element of area ∆A. For the sake of simplicity we will consider fluctuation in the number of carriers only, but the analysis can also be extended to include mobility fluctuation for the computation of the local current fluctuation. From UCCM (3), one can readily derive the relation between local charge density and threshold voltage fluctuations ToxIIoxI VnCQQCQ ∆−−=∆t'''''φ .  (7) The local fluctuation of the threshold voltage ∆VT is calculated from the conventional expression for the standard deviation [2] xWAV VTVTT ∆==∆222 σ  .   (8) Using (6), (7), and (8) we calculate (i∆A)2 and obtain the expression of 2DI∆  inserting this resultant into (5). With the aid of (2) the integration over the channel length in (5) is changed to the integration over the channel charge density given by ∫−=∆='''''22'22 1IDISDQQIItOXVTDoxDIdQQnCnLAICIφµσ . (9) Assuming, as in [14], Poisson statistics for the depletion charge fluctuations, then ( ) oioxDoxVT NCqxNCqA2'22'22 . ==   (10) where N is the average number of impurities per unit volume in the depletion region, xD is the depletion deep, and Noi=NxD is the effective number of impurities per unit area. Finally, using (10) and integrating (9) from source to drain results  −−='''''2222lnIDtoxIStoxDoxoiDIQnCQnCInCLNqIDφφµσ .  (11) The result in (11) is essentially the same as that derived for flicker noise in MOS transistors in [13]. This is because mismatch is a “dc noise” and the physical origin of both mismatch and flicker noise is fluctuation of either fixed charges or localized states along the channel.   5. MISMATCH MODEL IN TERMS OF INVERSION LEVELS  A useful alternative expression for (11) is obtained if the charge densities at source and drain are expressed in terms of the normalized forward and reverse currents if and ir. In the ACM model [10], the drain current is expressed as the difference between forward (IF) and reverse (IR) components )(),(),( rfSDGSGRFD iiIVVIVVIIII −=−=−=  (12) where IS = ½µC’ox nφt2(W/L) is the specific current, which is proportional to the geometric ratio W/L of the transistor. VG, VS, and VD are the gate, source, and drain voltages, respectively. if and ir are the normalized forward and reverse currents or inversion levels at source and drain, respectively. Note that in the saturation region, the drain current is almost independent of VD; therefore, if >>ir and ID ≅ IF. On the other hand, if VDS is low, then if ≅ ir. Using the relationship between inversion charge densities and currents [10], expression (11) can be rewritten as  ++−=rfrfoiDIiiiiWLNNID11ln12*22σ   (13) where we define N* as in [13, 15] qnCqQN toxIPφ''* =−=  .   (14) From weak to strong inversion in the linear region, if ≅ ir and (13) reduces to foiDIiWLNNID+=112*22σ .   (15) In weak inversion, if <<1; thus, the first order series expansion of (13) leads to 2*22WLNNIoiDID =σ     (16) for either saturation or nonsaturation. In saturation (ir→0), expression (13) can be written as  ( )ffoiDIiiWLNNID+=1ln2*22σ.   (17) VD Ml: W/x Mu: W/(L-x) VG 'IµWQ∆xR−=∆(a) VX gmsu.(Vx+∆∆ ∆∆VX) gmdl.Vx ∆Id VX+∆Vx i∆A (b) In weak inversion, if <<1 and (17) is almost insensitive to the current. In strong inversion, the normalized mismatch given by (17) reduces to the conventional expression if the logarithmic term is assumed to be constant.  Finally, the random errors due to edge effects can be modeled as in [1] resulting in a complete mismatch model ++++−=WBLBiiiiNNWLIWLrfrfoiDID11ln112*22σ (18) where BL and BW are the channel length and width mismatch factors due to edge effects.  6. MEASUREMENTS  Current mismatch of 24 NMOS 30µm x 1.2µm transistors was measured on a test circuit in the ES2 1.2µm CMOS DLM process, using the circuit shown in figure 2. MREF was kept the same for all measurements while the remaining 23 transistors were used as Mi for data acquisition.             Fig. 2. Test circuit: MREF is the reference transistor while Mi is the transistor under test. IB (VB, VD) is a current (voltage) source. Figure 3 presents the mismatch power normalized to the dc power (SD2(ID)/ID2) for drain-to-source voltage ranging from 20mV (linear region) to 1V (saturation), for different inversion levels. Simulated curves (dotted lines) have been determined from expression (13), with ir calculated through ACM long channel model expressions [10]. The average number of impurities per unit area (Noi) is estimated as 6.1x1012 cm-2; the resulting AVT calculated from (10) is about 29mV-µm. Specific current (IS) for the devices under test is 1.2µA. It should be emphasized that drain current mismatch results from geometrical and technological fluctuations; however, for most of the cases, the dominant factor that affects current mismatch can be associated with VT  mismatch.  In weak inversion (if = 0.01 and 0.1), mismatch is constant from linear to saturation region and independent of the inversion level, as predicted by (16). For if = 1, mismatch is approximately one half of the value measured for very weak inversion, as predicted in (15). For higher inversion levels (if = 10 and 100) and operation in the linear region, mismatch reduces by a factor of approximately 1/(1+if), compared to weak inversion. This value increases up to a plateau when saturation is reached, presenting a good agreement with expression (17) of our model. At this point one should compare our mismatch model with Pelgrom’s model [2]. If we were to use Pelgrom’s mismatch model together with the ACM model, the expression for the normalized mismatch power would be  22*22112++=foiDIiWLNNIDσ   (19) where the dependence on if is that of (gm/ID)2. Expressions (17) and (19) agree in weak inversion (if <<1), but for if=1000 (17) predicts a value 80% greater than (19). Explanation for this difference, arises from the distributed nature of the MOSFET. While Pelgrom’s model assumes a lumped VT for the MOSFET, our model assumes a distributed VT along the channel. As a consequence, for strong inversion and saturation, the part of the channel closer to the drain plays a less important role in the charge fluctuation along the channel than the part of the channel closer to the source. 10-110010-410-310-2VDS(V)SD2 (I D)/I D2if = 0.01 if = 0.1 if = 1 if =10 if = 100  Fig. 3. Normalized current mismatch power. Bulk was kept on zero voltage. (Measurements: —; simulation: ---.) Figure 4 shows the measured and simulated dependence of current matching on inversion level for linear (VDS=50mV) and saturation (VDS=1V) regions. For this measurement, transistors were paired in series for reduction of short channel effects, resulting in 12 transistor pairs per die, with 30µm x 2.4µm equivalent dimensions. Noi was estimated as 7.6x1012 cm-2, resulting in AVT of 32mV-µm. In agreement with our model, measurements show that matching is identical for either linear or saturated conditions under weak inversion. For inversion levels greater than one, mismatch decreases with inversion level more intensively for linear than for saturated condition. As can be seen, expression (13) describes current mismatch accurately for any inversion condition. In the bias range from 10µA to 100µA mismatch seems to increase for the linear region. This behavior is attributed to an effective reduction of the drain-to-source voltage due to voltage drops in contact and diffusion resistances. It is well know that bulk voltage also affects matching of MOS transistors [4]. Figure 5 shows relative mismatch for different values of bulk voltage for saturation (VDS=1V). Transistors were paired in series for reduction of short channel effects. In this case, one can suppose that Noi is modulated by  VGB. So, when bulk is more reverse biased, effective number of impurities per unit area increases under the gate, thus making Noi higher. It is clear in this figure that the greater the reverse bulk voltage, the greater the mismatch. As can be observed in Fig. 5, a forward-biased bulk improves matching. When the bulk is forward biased at 0.3V, an apparent reduction of mismatch occurs for bias current lower than 10nA. Such behavior is Mi MREF ID IB VB VG VD attributed to the action of the parasitic lateral bipolar transistor. The solid lines in figure 5 represent expression (13). Different values of Noi were chosen to fit the mismatch characteristics in weak inversion. 10-910-810-710-610-510-410-410-310-2IB(A)SD2(I D)/ID210-310-210-1100101102if  Fig. 4. Dependence of measured current matching on inversion level for linear ( - VDS=50mV) and saturation ( - VDS=1V) regions. Bulk was kept at zero volt. Solid lines show theoretical expression  (13). 10-910-810-710-610-510-410-410-310-210-1IB(A)SD2 (I D)/I D2 Fig. 5. Dependence of mismatch on bulk-to-source voltage in saturation (VDS=1V).  = -1.8V;  = -1.2V;  =  0V;  =+0.3V. Solid lines represent expression (13).  7. CONCLUSIONS  A mismatch model for the MOS transistor, continuous in all operation regions, has been developed. A physics based approach, based on fluctuation of carrier number, was used to integrate all the contributions of small mismatch elements along the transistor channel. This approach along with the description of the dc characteristics of MOSFET’s from the ACM model resulted in a compact easy-to-use formula for mismatch that covers any operating region. Results obtained are quite similar to those derived in [13] for 1/f noise, since the physical mechanisms at the origin of both phenomena are similar. Experimental results confirmed the accuracy of our model under various bias conditions. It is expected that this work will help designers understand and predict transistor mismatch in an accurate and easy way.  ACKNOWLEDGMENT  The authors are grateful to CNPq and CAPES, Brazilian agencies for scientific development, for their financial support.  REFERENCES  [1] J-B Shyu, G. C. Temes, and F. Krummenacher, “Random error effects in matched MOS capacitors and current sources”, IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 948-955, Dec. 1984. [2] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors”, IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, Oct. 1989. [3] F. Forti and M. E. Wright, “Measurements of MOS current mismatch in the weak inversion region”, IEEE J. Solid-State Circuits, vol. 29, no. 2, pp. 138-142, Feb. 1994. [4] M. J. Chen, J. S. Ho, and T. H. Huang, “Dependence of current match on back-gate bias in weakly inverted MOS transistor and its modeling”, IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 259-262, Feb. 1996. [5] J. A. Croon et al., “A comparison of extraction techniques for threshold voltage mismatch”, Proc. IEEE 2002 Int. Conference on Microelectronic Test Structures, pp. 235-240, 2002. [6] P. G. Drennan, and C. C. McAndrew, “Understanding MOSFET mismatch for analog design”, IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 450-456, March 2003. [7] M-F. Lan and R. Geiger, “Impact of model errors on predicting performance of matching-critical circuits, 43rd. IEEE Midwest Symp. on Circuits and Systems, pp.1324-1328, 2000. [8] M-F. Lan and R. Geiger, “Modeling of random channel parameter variations in MOS transistors”, IEEE International Symposium on Circuits and Systems (ISCAS), vol. I, pp.85-88, 2001. [9] S.Cristensson, I.Lundstrom, C.Svensson, “Low frequency noise in MOS transistors”, Solid-State Electron, vol.11, pp.797-812, 1968. [10] A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, “An MOS transistor model for analog circuit design”, IEEE J Solid-State Circuits, vol.33, no.10, pp.1510-1519, Oct.1998. [11] Tsividis, Y. P., “Operation and Modeling of the MOS Transistor”. McGraw Hill, 1999 [12] Y. Byun, K. Lee and M. Shur, “Unified charge control model and subthreshold current in heterostructure field effect transistors,” IEEE Electron Device Letters, vol. 11, no. 1, pp. 50-53, Jan. 1990. [13] A. Arnaud and C. Galup-Montoro, “A compact model for flicker noise in MOS transistors for analog circuit design”, IEEE Trans. Electron Devices, vol. 50, no.8, pp. 1815-1818, August 2003. [14] M. J. M. Pelgrom, “Low-power CMOS data conversion, Chap. 14 in Low-Voltage/Low-Power Integrated Circuits and Systems, E. Sánchez-Sinencio, A. G. Andreou, Eds. IEEE Press, York, 1999.  [15] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A physics-based MOSFET noise model for circuit simulators,” IEEE Trans. Electron Devices, vol. 37, pp. 1323-1333, May 1990. 

Consistent model for drain current mismatch in mosfets using the carrier number fluctuation theory

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Consistent model for drain current mismatch in mosfets using the carrier number fluctuation theory

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