'Institute of Electrical and Electronics Engineers (IEEE)'
Abstract
Optical switching offers the potential to significantly
scale the capacity of data center networks (DCN) with a
simultaneous reduction in switching time and power consumption.
Previous research has shown that end-to-end switching time,
which is the sum of the switch configuration time and the clock
and data recovery (CDR) locking time, should be kept within a few
nanoseconds for high network throughput. This challenge of low
switching time has motivated research into fast optical switches,
ultra-fast clock and amplitude recovery techniques. Concurrently,
the data rate between server-to-server and server-to-switch
interconnect is increasing drastically from the current 100 Gb/s
(4×25 Gb/s) to 400 Gb/s and beyond, motivating the use of high
order formats such as 50-GBaud four-level pulse-amplitude
modulation (PAM-4) for signalling. Since PAM-4 is more sensitive
to noise and distortion, digital equalizers are generally needed to
compensate for impairments such as transceiver frequency rolloff, dispersion and optical filtering, adding additional time for
equalizer adaptation and power consumption that are undesired
for fast optical switching systems. Here we propose and investigate
an equalizer state caching technique that reduces equalizer
adaptation time and computation power consumption for fast
optical switching systems, underpinning optically-switched DCNs
using high baud rate and impairment-sensitive formats. Through
a proof-of-concept experiment, we study the performance of the
proposed equalizer state caching scheme in a three-node optical
switching system using 56 GBaud PAM-4. Our experimental
results show that the proposed scheme can tolerate up to 0.8-nm
(100-GHz) instantaneous wavelength change with an adaptation
delay of only 0.36 ns. Practical considerations such as clock phase
misalignment, temperature-induced wavelength drift, and
equalizer precision are also studied