LEONE N.

LORIGA F.

MARIETTI, Piero

TRIFILETTI, Alessandro

English

Archivio della ricerca- Università di Roma La Sapienza

Non-linear Control of PLL Operation in Clock Recovery CircuitsNicola Leone, Francesco Loriga, Piero Marietti, Alessandro TrifilettiUniversità "La Sapienza", Dipartimento Ingegneria ElettronicaVia Eudossiana 18, I-00184, Roma, ITALYAbstract - In this paper the scheme of a new clock recovery circuit (CRC) based on the Charge-Pump PLL ispresented. In this scheme a non-linear control which monitores the amplitude level of the protoclock, is usedto open the PLL when the protoclock signal looses its well defined sinusoidal structure. The purpose of thiswork is twofold: to reduce the amount of sistematic jitter of the CRC without reducing the bandwith of thePLL, and to obtain a CRC with reduced sensitivity to bit-rate variations. The block scheme of the CRCrequires minor modifications with respect to the basic structure of a PLL-based CRC and it obtains evidentimprovements in the output jitter. The non-linear control makes a closed form analysis very difficult,therefore computer simulations have been performed to obtain an estimation of the mean squared jitter as afunction of the system parameters. In this paper we present the results in terms of output jitter for a CRC witha high degree of asymmetry in the prefilter section; the improvement we have obtained is of 6dB.Introduction - Clock recovery function in NRZ systems can be achieved by using a non-linear block toregenerate the bit-frequency reference and a high-Q component (passive filter or PLL) to filter the reference.The non-linear block can be achieved either by using a filter and a non-linear element [1,2] or by an edgedetector block [3]. As soon as a signal which contains a spectral component (protoclock [4]) has beenobtained, a band-pass element (postfilter) is needed to perform a filtering action and to increase SNR of theprotoclock. A PLL is often used to overcome mistuning effects and Q limitations [5,6] of passive postfilter. InFig. 1 the scheme of a CRC based on CP-PLL is shown [7,8].Fig. 1. Block scheme of the Clock Recovery Circuit based on Charge-Pump PLL.A careful analysis of the protoclock is necessary to find the input data sequences which can cause a jitterburst. In principle, the protoclock is a quasi-sinusoidal signal [9] which is affected only by amplitudemodulation and it could be used to drive a decision circuit. The lack of symmetry of the prefilter [10] causes aphase modulation in the protoclock which is the cause of the output jitter and therefore a postfilter becomesnecessary. To decrease the effect of the phase modulation it is possible to reduce the bandwidth of the PLL,reducing the capture range. A comparison between protoclock phase deviation and internal noise sources(In-Phase and In-Quadrature noise) shows that the phase modulation burst has to be related mainly toamplitude reduction of the useful component of the protoclock.We propose to use a non-linear control of the PLL operation to use the protoclock signal only when it hasa high instantaneous SNR, whereas during low SNR time intervals the non-linear control causes the rejectionof the protoclock and the PLL is disconnected.Protoclock analysis - The signal y(t) at the output of the squarer block can be obtained in terms of theimpulse response of prefilter and of the data stream {Cn}[11]:y(t) = yLF(t) + yHF(t), (1)y t x t x tLF c s( ) ( , ) ( , )= +122 2φ φo t , (2)y t x t x t f t x t x t sin f tHF c s b c s b( ) ( , ) ( , ) cos ( , ) ( , )= − + + +122 2 2 22 2φ φ π φ φ φ π φo t { } , (3)where the low-frequency components of the signal at the output of the prefilter arex t c g t nTcnnn c( , ) ( ) ( , )φ φ= − −=−∞+∞∑ 1 , (4)x t c g t nTsnnn s( , ) ( ) ( , )φ φ= − −=−∞+∞∑ 1 , (5)gc and gs are the low-frequency components of the impulse response of the prefilter, and φ is their referenceangle. By choosing the phase angle φ to satisfy the condition [11]x t x tc s( , ) ( , )φ φ = 0 (6)it becomes possible to separate the useful signal from In-Phase and In-Quadrature noise components. Thephase deviation due to the noise components is given by∆φ( ) tan' ( )' ( )tn tn tsc=+LNMOQP−11(7)where the noise components n'c, n's have been obtained dividing the noise component of the protoclock(Eq. 3) by the mean amplitude of the protoclock itself. In Tab. 1 the SNR of the protoclock as a function ofthe normalised detuning of the prefilter δ = ∆f/BW defined as the ratio of the frequency detuning to thebandwidth (-3dB) for the filter used in the simulations is shown.δ SNR (dB)0 220.05 200.125 12Tab. 1. SNR of the protoclock versus normalised detuning of the prefilter.Computer simulations have revealed that usually the worst condition from the point of view of the phasenoise of the protoclock is due to a decrease in the amplitude of the useful signal (In-Phase component), andnot by an increase in the In-Quadrature noise as it could be expected. In Fig. 2 the time plots of thenormalised In-Phase component and the phase deviation of the protoclock, obtained by a first orderButterworth filter tuned to a half of the bit-frequency, are shown. In the time periods while In-Phasecomponent is within -20 dB with respect its maximum value, the output phase deviation of the protoclock iswithin |∆φ| < 30°, therefore the protoclock shows a low phase-noise contribution.We propose a CRC made by a Charge-Pump PLL (CP-PLL) [7] and an amplitude control which opens theloop when the protoclock has a low SNR. The control signal could be the instantaneous amplitude of theIn-Phase component which is compared to its weighted mean to reveal low SNR condition. During a phasenoise burst the PLL has to remain on the latest value of the output phase (Hold state) to recover its filteringaction as the SNR has reached a sufficient value (Track state). For this application the Charge-Pump PLL isthe best candidate since it is a discrete-time system which receives an input signal (in terms of phase error)during the active periods of the PFD [7].The control signal - The transitions between Track and Hold states should be controlled by the In-Phasecomponent of the protoclock yHF(t)c t y t x t x tHF I c s( ) ( , ) ( , ) ( , )_= = −2122 2φ φ φo t. (8)As shown in Eqs. 2, 3 the spurious low-frequency component yLF(t) is another possible control signal sincethe power contribution of the xS component is usually negligible with respect to the xC onec t y t x t x tLF c s' ( ) ( ) ( , ) ( , )= = +122 2φ φo t.15 15.1 15.2 15.3 15.4 15.5 15.6-100-80-60-40-200t, usdBNormalized protoclock In-Phase component15 15.1 15.2 15.3 15.4 15.5 15.6-90-4504590t, usdegProtoclock phase deviationFig. 2. Time plot of the In-Phase component of the protoclock and protoclock phase deviation.The amplitude level of the control signal c'(t) has to be converted to a logic level TH to control the state ofthe loop (Track or Hold). The signal TH is defined by the following logical conditionTH c t Gc t= >' ( ) ' ( ) (9)and it can be obtained by using a low-pass filter, a gain element G and a threshold comparator. TheCharge-Pump PLL is easily completed by the non-linear control proposed as it can be seen in Fig. 3.Fig. 3. Non-linear Control block of the CRC proposed.The control lines U, D coming from the PFD are masked by the signal TH to lock the output phase of thePLL.The simulation set-up - To evaluate the effectiveness of the proposed solution we have performed computersimulations on the structure shown in Figs. 1, 3. The non-linear operation chosen to regenerate thebit-frequency line is performed by a prefilter and an ideal squarer. A first order Butterworth filter withBW = 20 MHz has been chosen as the prefilter for a bit-rate B=1Gbit/s. The input data sequence is a periodof a PRBS with 214-1 length without zero-filling and without additive noise. The output sequence has beenconsidered after the transient due to the phase/frequency acquisition; in these simulations phase noise of theVCO is not included. The parameters of the third order PLL are listed in Tab 2. A large number of prefiltershave been used to evaluate the effect of the control proposed here on protoclock signals obtained by slightlyasymmetrical pre-filters. Matlab and Simulink software tools have been used to perform time-domainsimulations with non-linear models of the CP-PLL. The output signal has been post-processed to evaluate themean squared value and the maximum value of the output jitter.BW Damping Factor Maximum Peaking200 KHz 1.73 0.62 dBTab. 2. Loop parameters of the PLL used in the simulations.Simulation results - The parameters chosen to evaluate the performance of CRC proposed are the maximumvalue of the output jitter and its mean squared value; the histogram of the jitter distribution is another keyfigure for this system. The gain imposed to the mean value of the control signal is a critical parameter for thisCRC since it sets a threshold level which controls the transitions between Hold and Track states. Thereforecomputer simulations have been performed by varying this gain and observing the output results in term ofrms output jitter. In high Bit-Rate applications (B > 622 Mbit/s) crystal oscillators are not available, thereforeit is very important to control both the ratio of time intervals in Track and Hold states and the longest timeinterval while the PLL is open to evaluate the influence of internal phase-noise of the VCO. In Fig. 4 the timeplot of the output jitter obtained from a prefilter with normalised detuning δ = 0 with non-linear control withcontrol gain G = 0.1 and without control are shown. The effectiveness of the solution proposed is apparent.The maximum output jitter is reduced by a factor of 1.5 and the rms value is reduced by a factor of 2.10 12 14 16 18 20 22 24 26-0.06-0.04-0.0200.020.040.06Output jitter, UIt, usFig. 4. Comparison between output jitter without non-linear control (dashed line) and with G = 0.1 (solidline).In Figs. 5, 6 the histograms obtained from the output jitter sequences without non-linear control and with anon-linear control, with G = 0.1, for a protoclock obtained by the means of a prefilter with normaliseddetuning δ = 0 are shown.-0.06 -0.04 -0.02 0 0.02 0.04 0.0600.10.20.30.40.50.60.70.80.91Output jitter, UIFig. 5. Output jitter histogram without non-linear control and δ = 0.-0.06 -0.04 -0.02 0 0.02 0.04 0.0600.10.20.30.40.50.60.70.80.91Output jitter, UIFig. 6. Output jitter histogram with control gain G = 0.1 and δ€= 0.In Fig. 7 the rms output jitter as a function of the control gain is shown (without prefilter detuning) and a bestvalue for the control gain is found (G = 0.15).0 0.05 0.1 0.15 0.2 0.250.0080.010.0120.0140.0160.0180.020.022 control gain  r.m.s. output jitter, UI Fig. 7. Rms value of the output jitter as a function of the control gain G.In Tab. 3 the results of simulations in terms of the output jitter as functions of control gain for three values ofprefilter detuning (δ=0, 0.05, 0.125) are listed.G = 0 G = 0.05 G = 0.1 G = 0.15 G = 0.2 G = 0.25δ = 0r.m.s.max.0.02150.05120.01270.03580.01050.03200.00970.03340.01110.03960.01340.0328δ = 0.05r.m.s.max.0.02550.07230.01630.04240.01800.04080.01770.03980.01550.03400.01180.0414δ = 0.125r.m.s.max.0.03760.10160.02940.08370.02640.06480.02340.05560.01900.04710.01710.0450Tab. 3. Maximum output jitter and rms jitter as functions of normalised detuning and control gain G.As the detuning is increased, the control gain required to achieve the minimum output jitter is increased aswell. We have evaluated the percentage of time (Toff/Ttot) and the maximum number of subsequent bits Nbwhile the PLL is open as functions of control gain G for the worst case of prefilter detuning (δ = 0.125). Inthe worst case (G=0.25) the PLL remains in the Track state for about 66% of the total time, and the maximumnumber of subsequent bit in the Hold state is 40. At the bit-rate under consideration, they correspond to 40 nswhich seems to be a short time with respect to time constants of 1/f noise of the VCO.G = 0 G = 0.05 G = 0.1 G = 0.15 G = 0.2 G = 0.25Toff/Ttot 0 0.0868 0.1670 0.2321 0.2862 0.3335Nb 0 21 27 35 37 40Tab. 4. Duty-cycle of the control signal TH (Toff/Ttot) and maximum number of bits Nb with PLLin the Hold state.Conclusion - In this paper a new architecture for Clock Recovery Circuits has been presented. A preliminaryanalysis aimed at separating useful signals from noise sources in the protoclock has been necessary. Alow-pass type control signal has been found to be the equivalent of the protoclock itself in terms of SNR andit is available in the symmetry protoclock. By using this control signal together with a Charge-Pump PLL, acomplete scheme of the CRC has been found, and it requires only minor modifications to the basic structure.Computer simulations have shown that the CRC proposed here is capable of reducing the output jitter in thepresence of strong phase modulations without reducing the bandwidth of the PLL. Further investigation willbe carried out to take the phase-noise contribution of the VCO into account.References[1] E. Roza, "Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission", IEEETrans. on Comm., Vol. Com-22, No. 9, pp. 1236-1249, Sep. 1974.[2] J. K. Holmes, "Tracking Performance of the Filter and Square Bit Synchronizer", IEEE Trans. on Comm.,Vol. COM-28, No. 8, pp. 1154-1158, Aug. 1980.[3] A. N. D'Andrea, U. Mengali, "Performance Analysis of the Delay-Line Clock Regenerator", IEEE Trans.on Comm., Vol. COM-34, No. 4, pp. 321-328, Apr. 1986.[4] T. T. Fang, "I and Q Decomposition of Self-Noise in Square-Law Clock Regenerators", IEEE Trans. onComm., Vol. COM-36, No. 9, pp. 1044-1052, Sep. 1988.[5] A. Buchwald, K. W. Martin, Integrated Fiber-Optics Receivers, Kluwer Academic Publishers, 1995.[6] P. R. Trischitta, E. L. Varma, Jitter in Digital Transmission Systems, Artech House, 1989.[7] F. M. Gardner, "Charge-Pump Phase-Lock Loops", IEEE Trans. on Comm., Vol. COM-28, No. 11, pp.1849-1858, Nov. 1980.[8] P. Ciammaichella, V. Ricchiuti, "About Optimum Slave Clock Bandwidth on SDH Equipment", to bepublished in the December 1995 issue of European Transaction on Telecommunications.[9] L. E. Franks, J. P. Bubrousky, "Statistical Properties of Timing Jitter in a PAM Timing RecoveryScheme", IEEE Trans. on Comm., Vol. COM-22, No. 7, pp. 913-920, July 1974.[10] A. Papoulis, The Fourier Integral and its Applications, McGraw-Hill Book Co., New York 1962.[11] N. Leone, P. Marietti, A. Trifiletti, "A Model of Symmetry Clock Recovery Circuit Based on I-QComponents", Int. Symposium on Synchronisation, Essen, Germany, 14-15 Dec. 1995.

Non linear control of PLL operation in clock recovery circuits

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Non linear control of PLL operation in clock recovery circuits

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