The purpose of this paper is to explore the trade-offs between IPC and maximum clock frequency in an in-order processor design. This work evaluates the impact on the performance and frequency of different pipeline optimizations. We target ASIC implementation using an advanced synthesis tool-flow with modern technology libraries. As a result, we can analyze the processor’s critical paths in a representative environment. In this paper, we analyze and modify Riscy, an in-order processor, taking into account the consequences of considering the ASIC target for this design. We have achieved a frequency of 1.3GHz and 2.03 CoreMark/MHz in the EEMBC CoreMark.Peer ReviewedPostprint (published version

Arvind

Doblas Font, Max

Moreto Planas, Miquel

Sonmez, Nehir

Wright, Andrew

English

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Microarchitectural Design-SpaceExploration of an In-Order RISC-VProcessor in a 22nm CMOSTechnologyMax Doblas⇤1, Andrew Wright†2,Nehir Sonmez⇤1, Miquel Moreto⇤1,Arvind†2⇤ High Performance Domain-Specific Architectures, Barcelona Supercomputing Center† Computer Science & Artificial Intelligence Lab,Massachusetts Institute of TechnologyABSTRACTThe purpose of this paper is to explore the trade-offs between IPC and maximum clock frequencyin an in-order processor design. This work evaluates the impact on the performance and frequencyof different pipeline optimizations. We target ASIC implementation using an advanced synthesistool-flow with modern technology libraries. As a result, we can analyze the processor’s criticalpaths in a representative environment. In this paper, we analyze and modify Riscy, an in-orderprocessor, taking into account the consequences of considering the ASIC target for this design.We have achieved a frequency of 1.3GHz and 2.03 CoreMark/MHz in the EEMBC CoreMark.1 IntroductionComputer architecture research in the academic community has generally focused on reduc-ing the number of clock cycles it takes to execute a program in a processor design. They useinstructions-per-cycle (IPC) as a performance metric but generally ignore the clock cycle du-ration. In the end, the real performance of a processor is measured in terms of instructions-per-second, which is the direct multiplication of the IPC and the clock frequency on a single-core processor. The right balance of these two parameters gives the maximum performance.Sometimes this is the most challenging part since the frequency is highly dependent on thetechnology chosen and the low-level optimizations applied by proprietary tools [AVLO17].Also, access to the tools and technology libraries is essential and hard to get. This paper aimsto improve an in-order processor called Riscy, a 5-stage in-order core developed at MIT, bytaking ASIC hardware synthesis into account. Many versions of Riscy have been synthesizedfor FPGAs and have been used in teaching.1E-mail: {max.doblas, nehir.somez, miquel.moreto}@bsc.es2E-mail: {acwright, arvind}@mit.eduACACES 2021 - Poster Abstracts  932 Original In-Order Riscy ProcessorRiscy in-order is a single issue 5-stage core. It implements the RV64I integer ISA along withthe complete implementation of the G and C extensions. It also implements the privilegedISA achieving to boot the Linux kernel successfully. Riscy in-order is written entirely inBluespec SystemVerilog (BSV), taking advantage of the modularity and atomicity given bythe properties of this language. The 5-stage pipeline is shown in Figure 1. The pipeline iscomposed of: a fetch stage, the decoder stage, the execution stage, the memory stage, andfinally, the write-back.3&,QVWUXFWLRQ&DFKH'DWD&DFKH'HFRGHU5HJLVWHU)LOHUHDGSRUW$/80LVSUHGLFWLRQ8QLW)HWFK 'HFRGH ([HFXWLRQ 0HPRU\ :ULWH%DFN%+78SGDWH5HDOLJQHU6FRUHERDUG0XO'LY8QLW)385HJLVWHU)LOH6FRUHERDUGZULWHSRUW%UDQFK3UHGLFWLRQ%7%Figure 1: Diagram of the original Riscy v1 pipelineIf we take a more in-depth vision of the core, Riscy implements BHT and BTB branchpredictors to improve PC generation. Also, all the forwarding has been implemented toreduce the data dependencies. The caches are 16K Bytes, 4-way associative, VIPT with onecycle of latency. All the memory arrays inside the caches are implemented using SRAMs.This design has two well-known spots that cause a considerable delay if the FPU andthe MULT/DIV units are ignored. These two critical points are located in the two caches. Inparticular, in the tag comparison on the second cycle of the access. It is due to two factors;the considerable access time of the SRAM itself and the comparison of the SRAM outputtags with the physical tag from the TLB. Thus, these two actions, which are performed inseries, introduce a huge delay that can be propagated if the cache’s output is not registered.To verify the hypothesis made, we have performed 22nm ASIC syntheses of the Riscy.The results show a critical path that starts on the instruction cache tag array as we expected.The maximum frequency is 667 MHz and 633 MHz with the bypasses implemented.3 7-stage High Frequency Riscy pipelineOne of the most critical points in the pipeline is the front-end of the design. The SRAMinside the instruction cache has an output delay that consumes a huge part of the clockcycle. It is necessary to add a register at the output of the instruction cache to avoid furtherpropagation of this delay. Also, we decided to break the decoder stage in two to reduce thenumber of operations done in series in this stage and the control logic of this stage. The newfront-end is shown on Figure 2. With the last modifications, all the major critical paths of theFront-End have been removed. Although, now the pipeline has seven stages. The incrementof stages has an impact on performance because the PC redirections have a more significantcycle penalty.ACACES 2021 - Poster Abstracts 943&,QVWUXFWLRQ&DFKH)HWFK%7%8SGDWH3UHGLFWLRQ%7%5HDOLJQHU3UH'HFRGHU%+78SGDWH3UHGLFWLRQ%7+0LVSUHGLFWLRQUHGLUHFWLRQ)HWFK )HWFK'DWD&DFKH'HFRGHU5HJLVWHU)LOHUHDGSRUW$/80LVSUHGLFWLRQ8QLW'HFRGH ([HFXWLRQ 0HPRU\ :ULWH%DFN6FRUHERDUG0XO'LY8QLW)385HJLVWHU)LOH6FRUHERDUGZULWHSRUWFigure 2: Block diagram of the new Riscy back-endIn a similar way to the instruction cache, it is necessary to avoid all the data paths gener-ated for the data cache. We have decided to register the output of the SRAMs. We modifiedthe data cache by adding a register on the output of each SRAMs to cut the delay propaga-tion. The critical paths should be removed. However, all the memory and atomic instructionshave a penalty of one cycle, which significantly impacts performance since each memory oratomic instruction is stalling the pipeline one cycle. With these changes, the critical path wassolved. However, we have noticed that the extra latency on the data cache had a significantnegative impact on performance. However, we can hide this extra latency if the access to thedata cache is started in the execution stage.4 Evaluation and ResultsIn this section, we have evaluated the different versions of the design: Riscy v1: Originalversion of the core; Riscy v1-B: Riscy v1 with bypasses implemented.Riscy FE: it has thenew front-end without bypasses implemented; Riscy FE-B: Riscy FE with the bypasses im-plemented; Riscy FE-B-DC: the Riscy FE-B with the two-cycle latency data cache; Riscy v2:It is the final version of Riscy proposed in this project.For the evaluation, we used the EEMBC CoreMark. For the clock frequency and criticalpath analysis, we used an ASIC target synthesis done with the Genus 19.11-s087_1 fromCadence. We are using the 22FDX GlobalFoundries technology node. The standard cell li-braries used in all the analysis has 8-tracks, low Vt, a 104 CPP with the typical corner at25 C, and a power supply of 0.8 V.4.1 Frequency and IPC Evolution of RiscyFirst of all, we comment and analyze the evolution of the performance in the different ver-sions of the Riscy core. Figure 3 shows the results of IPC (Coremark/MHz) and the maxi-mum frequency of each version of the Riscy core. Also, it shows the performance (Coremark,much is better) of each design version.Riscy v2 improves the maximum clock frequency by 39%, and the IPC by 15% comparedto the original Riscy v1, making the Riscy v2 60% faster than Riscy v1. However, directlycomparing Riscy v1 with Riscy v2 is not fair because they have different IPC optimizations.To make an apple to apple comparison, we need to compare the Riscy v1-B with Riscy v2 asboth implement the bypass optimization. Riscy v2 has a clock frequency that is 47% faster,but with a 9% IPC reduction, resulting in a 34% overall performance improvement. Also, wesynthesize Riscy v2 using different combinations of 8-track cells with low and superlow Vt.ACACES 2021 - Poster Abstracts  95Figure 3: Evolution of the performance of the Riscy core designs. On the left side, there arethe IPC and frequency results. On the right side there is the overall performance results.In the 8-track super-low Vt configuration, Riscy v2 achieves 930 MHz, 1353 MHz, and 1658MHz in slow, typical, and fast corners.5 ConclusionsIn this project, we have explored the design space of the Riscy core for a modern 22nm ASICtechnology target. The final design has a performance improvement of around 60% to theoriginal Riscy design. Compared to the original Riscy design with the same IPC optimiza-tions, around 34% performance improvements are achieved. This improvement is mainlyachieved thanks to the improved maximum clock frequency of the design. Riscy v2 has amore mature 7-stage pipeline taking into account the SRAM timing limitations. It scores a2.03 CoreMark/MHz in the EEMBC CoreMark benchmark, staying very close to the perfor-mance achieved by some of the best academics cores as Rocket [Asa16] and Ariane [ZB19].Moreover, it can achieve more than 1.3 GHz in a typical PVT corner using a technology nodeof 22nm from GlobalFoundries.It would also be interesting to implement a superscalar issue in Riscy and apply the sameanalysis performed in this project. Since the complexity in the core increases considerably,the new critical paths probably would not be related to the caches. Moreover, it will beinteresting to apply the same analysis to the RiscyOO out-of-order design [ZWBA18].References[Asa16] Krste AsanoviÄ. The rocket chip generator. Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, Apr 2016.[AVLO17] L. AmarÃº, P. Vuillod, J. Luo, and J. Olson. Logic optimization and synthesis:Trends and directions in industry. In Design, Automation Test in Europe ConferenceExhibition (DATE), 2017, pages 1303–1305, 2017.[ZB19] F. Zaruba and L. Benini. The cost of application-class processing: Energy andperformance analysis of a linux-ready 1.7-ghz 64-bit risc-v core in 22-nm fd-soi technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,27(11):2629–2640, Nov 2019.[ZWBA18] S. Zhang, A. Wright, T. Bourgeat, and A. Arvind. Composable building blocksto open up processor design. In 2018 51st Annual IEEE/ACM International Sym-posium on Microarchitecture (MICRO), pages 68–81, 2018.ACACES 2021 - Poster Abstracts 96

Microarchitectural design-space exploration of an in-order RISC-V processor in a 22nm CMOS technology

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Microarchitectural design-space exploration of an in-order RISC-V processor in a 22nm CMOS technology

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