The absorption of power & SRAM’s speed are major concern which followed several designs in accordance to the minimal absorption of power. The main concern of this document is on decadence of power while operation of Write is executed in 6-T CMOS SRAM also while operation of read as well. In this paper, an extra transistor is invaded in cell of SRAMs which will be regulate total capacitance while execution of read & write operations & also optimize the capacitance so eventually leads to bring down decadence in power. In this document we mainly focus on decadence of power during short circuits also the fluctuating decadence of power which can also be termed as power which is dynamic. The tool of Tanner is deployed to evaluate the circuitry, the schema of cell of SRAM is formulated on S Edit & simulation of net list is furnished by making use of T Spice & also assessment of waveforms is done by W Edit. The characterization of circuitry is done by making use of technology of 45 nm which furnish a voltage of 1.2V. The outcomes are put in contrast to traditional 6T SRAM & 7T SRAM which also characterizes the same in this document. Also we implement a cell with less power that is comprised of an additional transistor & also the gate of that transistor will regulate the operations of write & read of information when we implement function of write operation, that additional transistor will execute function of write & additional transistor will shorten the section in ground & Vdd & save the power
