'Institute of Electrical and Electronics Engineers (IEEE)'
Abstract
Journal ArticleMost high level synthesis tools for asynchronous circuits take descriptions in concurrent hardware description languages and generate networks of macromodules or handshake components. In this paper we describe a peephole optimizer for such macromodule networks that often effects area and/or time improvements. Our optimizer first deduces an equivalent black-box behavior for the given network of macrmodules using Dill's trace-theoretic parallel composition operator. It then applies a new procedure culled Burst-mode reduction to obtain burst-mode machines, which can be synthesized into gate networks using available tools. Since burst-mode reduction can be applied to any macromodule network that is delay-insensitive as well as deterministic, our optimizer covers a significant number of asynchronous circuits especially those generated by asynchronous high level synthesis tools
