Since frame resolution of modern video streams is rapidly growing, the need for more complex and efficient video compression methods arises. H.265/HEVC represents the state of the art in video coding standard. Its architecture is however not completely standardized, as many parts are only described at software level to allow the designer to implement new compression techniques. This paper presents an innovative hardware architecture for the Steerable Discrete Cosine Transform (SDCT), which has been recently embedded into the HEVC standard, providing better compression ratios. Such technique exploits directional DCT using basis having different orientation angles, leading to a sparser representation which translates to an improved coding efficiency. The final design is able to work at a frequency of 188  MHZ, reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 × 4320) with a frame rate of 60  Hz, which is one of the best resolutions supported by HEVC

B Zeng

G Fracastoro

GJ Sullivan

H Sun

I Daubechies

PK Meher

RS Oliveira

Z Chen

English

Sole, Luigi

Peloso, Riccardo

Capra, Maurizio

Ruo Roch, Massimo

Masera, Guido

Martina, Maurizio

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

16 July 2022POLITECNICO DI TORINORepository ISTITUZIONALEVLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT) / Sole, Luigi; Peloso, Riccardo; Capra, Maurizio;Ruo Roch, Massimo; Masera, Guido; Martina, Maurizio. - ELETTRONICO. - 627:(2020), pp. 137-143. ((Interventopresentato al convegno ApplePies Applications in Electronics Pervading Industry, Environment and Society tenutosi aPisa nel September 11-13, 2019 [10.1007/978-3-030-37277-4_16].OriginalVLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT)Springer postprint/Author's Accepted ManuscriptPublisher:PublishedDOI:10.1007/978-3-030-37277-4_16Terms of use:openAccessPublisher copyrightThis version of the article has been accepted for publication, after peer review (when applicable) and is subject toSpringer Nature’s AM terms of use, but is not the Version of Record and does not reflect post-acceptance improvements,or any corrections. The Version of Record is available online at: http://dx.doi.org/10.1007/978-3-030-37277-4_16(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/2847345 since: 2020-10-23T14:47:45ZSpringer, ChamVLSI architectures for theSteerable-Discrete-Cosine-Transform (SDCT)Luigi Sole, Riccardo Peloso, Maurizio Capra, Massimo Ruo Roch, GuidoMasera, and Maurizio MartinaPolitecnico di TorinoAbstract. Since frame resolution of modern video streams is rapidlygrowing, the need for more complex and efficient video compressionmethods arises. H.265/HEVC represents the state of the art in videocoding standard. Its architecture is however not completely standard-ized, as many parts are only described at software level to allow thedesigner to implement new compression techniques. This paper presentsan innovative hardware architecture for the Steerable Discrete CosineTransform (SDCT), which has been recently embedded into the HEVCstandard, providing better compression ratios. Such technique exploitsdirectional DCT using basis having different orientation angles, leadingto a sparser representation which translates to an improved coding ef-ficiency. The final design is able to work at a frequency of 188 MHz,reaching a throughput of 3.00 GSample/s. In particular, this architec-ture supports 8k UltraHigh Definition (UHD) (7680x4320) with a framerate of 60 Hz, which is one of the best resolutions supported by HEVC.Keywords: Video Coding, Discrete Cosine Transform, Directional Trans-form, VLSI1 IntroductionIn recent years, a large effort has been devoted to the field of video compressionto cope with the increasing demand of high resolution multimedia contents. Thelatest standard proposed by ITU-T and ISO/IEC groups is the H.265/HEVCcompression algorithm [8]. It extensively employs inter-frame and intra-frameprediction to exploit the temporal and the spatial redundancies present in videostreams. H.265/HEVC requires computational load to detect and process intramode, so many efforts have been done in order to lower the complexity [6] ofthe detection phase. The difference between the predicted block and the actualblock of pixels is called residual block and it is lossly coded taking advantageof transforms (Discrete Sine Transform, DST, and Discrete Cosine Transform,DCT) and quantization. While the DST is used only for the smallest blocksize, namely 4x4 pixels, the DCT is used for all the other sizes, typically up to32x32. Chen et al. [1] has shown how to reduce the complexity of the IntegerCosine Transform enabling solution up to 64x64. Since DCT is increasing incomplexity and computational load, faster and low-power architectural solutionssuch as [9] and [7] are required. Recently, G. Fracastoro et al. [3] proposed a2 L. Sole et al.directional DCT, called Steerable DCT (SDCT), which is better suited thanDCT to compress directional data. The SDCT is based on the work of B. Zenget al. [10] and makes possible to divide the directional cosine transform into atraditional DCT followed by a geometrical rotation. The kernels used for theSDCT are different from the DCT ones as they depend on the steering angle,with the limit case of 0 degrees rotation for which the SDCT coincides withthe DCT. This paper presents a low power hardware accelerator for SDCT ableto reach the throughput required by HEVC for the 8k UltraHigh Definition of7680x4320 pixels. At first the architecture is analysed in Section 2 and then theSection 3 will present the obtained results for the basic SDCT accelerator andsome implementations stemming from it.2 Architectural implementationWhile the 2D-DCT employed in HEVC is an inherently separable operation, theSDCT must be computed all at once. The complexity of a transform that is notseparable is far greater than a separable one, so this may be a big drawbackfor the implementation. However, the complexity can be decreased drasticallyby splitting the SDCT in two parts, namely a separable 2D DCT followed bysome rotations, and then by computing the separable transform before applyingrotations, as reported in [4]:x̃ = T (θ)x = R(θ)Tx = R(θ)x̂ (1)where x are the input samples, x̂ are the results obtained by applying the Ttransform matrix, R(θ) is the rotation matrix, while x̃ is the result of the SDCT.The SDCT can be thus implemented as a DCT followed by a steering transfor-mation. The DCT part can be implemented as suggested in the literature, forexample using a folded architecture [5], and then applying rotations when allthe samples returned by the 2D-DCT are available. This means that the steer-ing part of the architecture, which handles the rotations, has to work faster thanthe DCT. This issue has been addressed in this work and one of the possible so-lution is to define two clock regimes, one for the 2D-DCT and one, faster, for thesteering part, in order to comply with the throughput offered by the 2D-DCTtransform block. A FIFO memory between the two parts acts as a buffer memory.The whole structure is depicted in Figure 1. The 2D-DCT block is based on thearchitecture proposed in [5] by Meher et al., which is very efficient, especiallyin the folded fashion, and scalable to transforms of size 4, 8, 16 and 32. Thesteerable part is shown in Figure 2. It is composed by an input memory (IM),an output memory (OM) and the lifting blocks that perform the rotation [2].Some multiplexers are used to bypass the lifting blocks for the case of no rota-tion, returning directly the result given by the DCT. The IM is required also toreorder the samples as the steering process is computed on the custom zig-zagorder, given in Figure 3, that is different from the classic zig-zag ordering, as thevectors are rotated in pairs with respect to the diagonal elements. Rotation byVLSI architectures for the SDCT 3Fig. 1. Whole SDCT structurelifting scheme:(cos θ sin θ− sin θ cos θ)=(1 1−cos θsin θ0 1)(1 0− sin θ 1)(1 1−cos θsin θ0 1)(2)The rotation matrix is decomposed in the multiplication of other three rotationmatrices, in such a way the resulting structure, shown in Figure 4, presents alower complexity. Indeed, this implementation requires only three multipliers,while the original rotation matrix would need four multipliers to achieve thesame result. In order to further simplify the architecture, the multiplication forP and U coefficients from Equation 2P =1 − cos θsin θ(3)U = − sin θ (4)in Figure 4 is implemented as shift and add, as the number of possible rotationangles have been fixed to 8 (from 0, no rotation, to 7), as reported as optimumin [4] by M. Masera et al. The steerable block thus introduces 2×N clock cyclesof latency for the reordering stage plus 4 clock cycles due to the internal pipeline.Therefore, in the event that all the SDCT have a length N=32, the latency isequal to 68 clock cycles, which corresponds to the worst case.2.1 Reduced SDCT architecturesThe unit presented so far is able to compute SDCT of lengths 4, 8, 16 and 32.This type of structure has been designed to be implemented inside the HEVCstandard. Anyway, this algorithm could be also used for video compression stan-dards with lower constraints and for image compression standard, such as JPEG.Therefore, two reduced SDCT unit have also been developed. The first is ableto compute SDCT of length 4, 8 and 16, named SDCT-16, while the secondis capable of computing SDCT of length 4 and 8, named SDCT-8. These twounits have a reduced throughput of 50% and 75% respectively, so they have a4 L. Sole et al.Fig. 2. Steerable block structureFig. 3. Zig-zag scanning order Fig. 4. Lifting-based rotationparallelism of 16 or 8 data instead of 32, reducing the size of all the memories.In particular the length of both rows and columns of all memories is halved inthe SDCT-16 unit, while is four time lower in the SDCT-8 unit with respect toSDCT-32. As a result the area occupation of these units is much lower than theSDCT-32 one. Moreover, just one clock domain has been used for both DCTand steerable block.3 ResultsIn order to satisfy the HEVC speed requirements for a video resolution of7680× 4320 and a frame rate of 60 fps, the proposed structure needs a through-put of almost 3 GSample/s. As discussed in Section 2, the folded version pre-sented in [5] has been implemented since this approach guarantees the requiredthroughput. This structure has a processing rate of 16 pixels per cycle, thereforethe architecture needs a frequency of at least 187 MHz (2.99 × 109/16 MHz).Clock gating has been enabled for the synthesis, leading to a smaller area andlower power consumption. The technology employed for the synthesis is the UMC65 nm. The following architectures have been considered and synthesized:– two-dimensional DCT– SDCT– reduced SDCT-16– reduced SDCT-8VLSI architectures for the SDCT 5For the SDCT implementation, several clocks have been tested for the steer-ing part, namely 1x, 2x, 4x and 8x. By increasing the Steerable unit frequencyit is possible to decrease the parallelism and consequently the number of in-put/output ports of the buffers.Cell 1x total area 2x total area 4x total area 8x total areaSDCT 4337744 µm2 3042226 µm2 1608759 µm2 1301522 µm22D-DCT 438866 µm2 601970 µm2 455150 µm2 474167 µm2IM 1401523 µm2 820032 µm2 495856 µm2 335932 µm2OM 2377837 µm2 1418162 µm2 482048 µm2 319037 µm2FIFO 86542 µm2 110594 µm2 113008 µm2 110604 µm2ROM 5895 µm2 22228 µm2 13227 µm2 33223 µm2Table 1. SDCT area occupation for different clock regimesIt can be noticed that by reducing the data parallelism of the Steerableunit, the size of the input memory (IM) and output memory (OM) decreasesconsiderably, while the size of all the other sub-blocks slightly increases.Power Internal Switching Total dynamic Leakagebasic DCT 36.55 mW 17.72 mW 54.47 mW 33 µWclock gated DCT 21 mW 12.52 mW 33.52 mW 30 µWbasic SDCT 290.47 mW 60.33 mW 350.88 mW 106 µWclock gated SDCT 88.71 mW 59.85 mW 148.67 mW 94 µWclock gated SDCT-16 27.86 mW 28.97 mW 56.85 mW 27 µWclock gated SDCT-8 6.56 mW 7.20 mW 14.17 mW 7 µWTable 2. Estimated power consumption at 188 MHzIn literature there are no other SDCT hardware architectures, so it is notpossible to make comparisons. However, Table 3 presents an overview of theobtained results. As it can be noticed, the area and power results of the SDCT-Architecture DCT SDCT SDCT-16 SDCT-8Technology (nm) 65 65 65 65Frequency (MHz) 188 188 188 188Power (mW) 33.52 148.67 56.85 14.17Throughput 2.992G 2.992G 1.496G 0.748GArea (mm2) 0.321 1.427 0.444 0.110Table 3. Overview of the obtained architectures16 are around 60% smaller than the complete SDCT. On the other hand, theSDCT-8 area is around 75% smaller than the SDCT-16 and 90% smaller thanthe complete SDCT while the throughputs are reduced respectively by 50% and75%. Finally, comparing the DCT and the SDCT architecture we can observethat the hardware overhead to support up to N=32 is very large. However,removing the hardware support for the steering part with N=32 (SDCT-16),the area becomes comparable with the one of the DCT. As a consequence, thissolution can be of interest to increase the rate-distortion performance [4].6 L. Sole et al.4 ConclusionThis paper provides an efficient and compact hardware architecture acceleratorfor the SDCT algorithm to be used in the HEVC algorithm. Many of the designchoices explained above present an optimized approach, such as the lifting-basedapproach, in which the hardware resources are reduced to a minimum. Moreover,the flexibility showed by this architecture makes it appealing for a wide rangeof applications, being able to work with different coding formats. The proposedSDCT framework is able to cope with 8k UltraHigh Definition (UHD) (7680 ×4320pixels) with a frame rate of 60 Hz for the 4:2:0 YUV format, which is oneof the highest resolution supported by HEVC. The steerable DCT is a viablesolution to improve compression efficiency, as reported in [4]. Further work willcover the integration of the proposed accelerator in a complete HEVC frameworkto validate the performances in a real case scenario.References1. Chen, Z., Han, Q., Cham, W.: Low-complexity order-64 integer cosine transformdesign and its application in hevc. IEEE Transactions on Circuits and Systems forVideo Technology 28(9), 2407–2412 (Sep 2018)2. Daubechies, I., Sweldens, W.: Factoring wavelet transforms into lifting steps.Journal of Fourier Analysis and Applications 4(3), 247–269 (May 1998), https://doi.org/10.1007/BF024760263. Fracastoro, G., Fosson, S.M., Magli, E.: Steerable discrete cosine transform. IEEETransactions on Image Processing 26(1), 303–314 (Jan 2017)4. Masera, M., Fracastoro, G., Martina, M., Magli, E.: A novel framework for de-signing directional linear transforms with application to video compression. In:ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech andSignal Processing (ICASSP). pp. 1812–1816 (May 2019)5. Meher, P.K., Park, S.Y., Mohanty, B.K., Lim, K.S., Yeo, C.: Efficient integer dctarchitectures for hevc. IEEE Transactions on Circuits and Systems for Video Tech-nology 24(1), 168–178 (Jan 2014)6. Ogata, J., Ichige, K.: Fast intra mode decision method based on outliers of dctcoefficients and neighboring block information for h.265/hevc. In: 2018 IEEE In-ternational Symposium on Circuits and Systems (ISCAS). pp. 1–5 (May 2018)7. Oliveira, R.S., Cintra, R.J., Bayer, F.M., da Silveira, T.L.T., Madanayake, A.,Leite, A.: Low-complexity 8-point dct approximation based on angle similarity forimage and video coding. Multidimensional Systems and Signal Processing 30(3),1363–1394 (Jul 2019), https://doi.org/10.1007/s11045-018-0601-58. Sullivan, G.J., Ohm, J., Han, W., Wiegand, T.: Overview of the high efficiencyvideo coding (hevc) standard. IEEE Transactions on Circuits and Systems forVideo Technology 22(12), 1649–1668 (Dec 2012)9. Sun, H., Cheng, Z., Gharehbaghi, A.M., Kimura, S., Fujita, M.: Approximate dctdesign for video encoding based on novel truncation scheme. IEEE Transactionson Circuits and Systems I: Regular Papers 66(4), 1517–1530 (April 2019)10. Zeng, B., Fu, J.: Directional discrete cosine transformsa new framework for imagecoding. IEEE Transactions on Circuits and Systems for Video Technology 18(3),305–313 (March 2008)

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT)

Crossref

https://iris.polito.it/bitstream/11583/2847345/1/main.pdf

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT)

Abstract

Similar works

Full text

Available Versions

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

Crossref