Real Time Systems are integrated with physical processes such as sensors and actuators. Real Time Systems are time critical and hence they must be able to handle upper time bounds along with the correct functional behavior. The correct implementation of the functionality specified in the software is done using the Instruction Set Architecture (ISA) by the processor. But, neither the software nor ISA has a time measuring or time controlling role here and if time properties have to be guaranteed designers are required to reach beneath the abstraction layers which increases design complexity and effort.
This thesis proposes a solution to bring control over time to the software by examining the Instruction Set Architecture (ISA) layer. The ISA defines the contract between software instructions and hardware implementations. But ISAs usually do not have timing properties imbibed in them. Hence, this work will investigate the instructions extension feature offered by RISC-V platform to allow programs to specify execution time properties in software. These include the ability to specify a minimum execution time for code blocks, and the ability to detect and handle missed deadlines from code blocks that exhibit variable execution times.
This thesis investigates the RISC-V CPU named VexRiscV built by Charles Papon on the platform SpinalHDL where in which Custom Instructions would be added into the RISC-V ISA through the instruction extension featured allowed by the RISC-V platform. This was implemented and tested on an Arty A7-100 FPGA with the help of Xilinx tools
