Bøgholm, Thomas

Luckow, Kasper Søe

Thomsen, Bent

English

    Aalborg UniversitetSupporting Development of Energy-Optimised Java Real-Time Systems usingTetaSARTSLuckow, Kasper Søe; Bøgholm, Thomas; Thomsen, BentPublication date:2013Document VersionEarly version, also known as pre-printLink to publication from Aalborg UniversityCitation for published version (APA):Luckow, K. S., Bøgholm, T., & Thomsen, B. (2013). Supporting Development of Energy-Optimised Java Real-Time Systems using TetaSARTS. Poster presented at 19th IEEE Real-Time and Embedded Technology andApplications Symposium, Philadelphia, Pennsylvania, United States.General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright ownersand it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.            ? 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You may freely distribute the URL identifying the publication in the public portal ?Take down policyIf you believe that this document breaches copyright please contact us at vbn@aub.aau.dk providing details, and we will remove access tothe work immediately and investigate your claim.Downloaded from vbn.aau.dk on: December 26, 2020Supporting Development of Energy-OptimisedReal-Time Java Systems using TetaSARTSKasper Søe Luckow, Thomas Bøgholm, and Bent ThomsenDepartment of Computer Science, Aalborg University, Denmark{luckow,boegholm,bt}@cs.aau.dkMotivationIt is well-known, that the traditional Java run-timeis unsuited for use in embedded real-time systems,which is attributed issues such as the lack of high-resolution real-time clocks and timers, insufficientthread semantics, and, most notably, memorymanagement, which is traditionally handled by agarbage collector whose execution is highly unpre-dictable. However, with emerging standards suchas the Real-Time Specification for Java (RTSJ)and the Safety Critical Java (SCJ) profile, theseissues have been accounted for, thereby achievinga significant step towards use in embedded real-time systems development.Having a suitable programming model as intro-duced by e.g. SCJ and RTSJ is not the only com-ponent in making Java a viable technological al-ternative and competitor to C in the embeddedreal-time systems domain. Equally important isthe complementation of tools and analyses thatsupport the development, and for verification pur-poses. For real-time systems, the latter comprisesfunctional correctness, but also temporal correct-ness, which is the focus of this work.ContributionsDoneExecutingTaskDeadlineOverrunrun[pID]!ReadyToBeScheduledrun[pID]?CheckForOffsetGO?releasedTime <= offsetreleasedTime <= deadlinereleasedTime <= periodreleasedTime == periodreleasedTime <= deadlineschedulable[pID] = true,releasedTime = 0,insert_task_in_scheduler(pID),wcrt = 0schedulable[pID] = false,task_done_scheduler(),wcrt = 0offset != 0releasedTime > deadlineoffset == 0releasedTime == offsetGO?Fig. 1: Timed Automaton monitor-ing the state of the associated task.UtilisationMonitorutil' == !idling && idle' == idlingFig. 2: Utilisa-tion monitor.We put forward the TetaSARTS tool whose capa-bilities include:Schedulability Analysis The analysis is approachedas a reachability, model checking problem by de-termining whether the Timed Automata modelsatisfies the specification A not deadlock. Adeadlock can only be reached, if there exists asimulation reaching the DeadlineOverrun loca-tion for any of the real-time tasks (see Fig. 1).Clock Frequency Adjustment The analysis facili-tates adjustment of the clock frequency. Usinga technique such as the bisection method, theappropriate clock frequency can be determinedwhile still ensuring schedulability. Thus, poten-tial energy reductions can be identified.Worst-Case Response Time Analysis The TimedAutomata model facilitates Worst-Case ResponseTime (WCRT) analysis to be conducted takinginto account blocking time. Using the sup-queryextension of the Uppaal specification language,the maximum observed value of a clock variablecan be found. Hence, e.g. for periodic tasks,WCRT analysis can be conducted using the spec-ification sup{periodicThread .ExecutingTask} :periodicThread .wcrt (see Fig. 1).Processor Utilisation/Idle Time Analysis Addingthe Timed Automaton shown in Fig. 2 allowsmonitoring the utilisation and idle time of theprocessor using the specification sup : util , idle.TetaSARTSSCJ ProgramSCJ ProgramJava RT SystemJavac, ECJ, GCJ, ...SCJ ProgramSCJ ProgramJava BytecodeTetaSARTSTIRTIR BuilderTIR Analyser and DecoratorUPPAAL NTA GeneratorUPPAAL NTA Analyser and OptimiserProgram NTANTA SynthesiserAnalysis SpecifierJVM NTA GeneratorJVM NTAHardware NTAJVM ExecutableUPPAAL Verification EngineNTA SystemFig. 3: TetaSARTS.Program NTA LayerJVM NTA LayerHardware NTA LayerScheduler TAPeriodic Task Controller TASporadic Task Controller TASporadic Task NTAPeriodic TaskNTA......Periodic Task Controller TAPeriodic TaskNTAExplicit Execution Environment ModelInline Execution Environment ModelFig. 4: Resulting NTA.TetaSARTS is a fully automated tool for conduct-ing timing analyses of SCJ Java Bytecode pro-grams taking into account the execution environ-ment (see Fig. 3 for an overview). It accommo-dates hardware implementations of the JVM, andtraditional execution environments with a softwareimplementation of the JVM including the hostinghardware. It supports both periodic and sporadicreal-time tasks, and from these, it generates TimedAutomata simulating their control flow. The struc-ture of the model and the communication betweenthe Timed Automata using synchronisation actionsis shown in Fig. 4. The analyses are performed us-ing the Uppaal model checker.Timed AutomataTimed Automata are generated from Java Byte-code by identifying the event handlers of the real-time tasks such as the one in Listing 1.public class MethaneCtrl extends PeriodicEventHandler {public void handleAsyncEvent() {if ( this .methaneSensor.isCritMethaneLvlReached())this .waterpumpActuator.run();elsethis .waterpumpActuator.stop();}}Listing 1: SCJ event handler periodically firinghandleAsyncEvent().From Java Bytecode, the control flow graph is re-constructed, producing the intermediate represen-tation, TIR, on which various analyses and opti-misations are applied. TIR is then translated toTimed Automata (see Fig. 5).ifeq277getfield276iload_1278 aload_0279jvm_execute!jvm_execute!jvm_execute!jvm_execute!iload_1306 aload_0307running[tID] == truerunning[tID] == truejvm_instruction = JVM_GETFIELDjvm_instruction = JVM_IFEQrunning[tID] == truerunning[tID] == truerunning[tID] == truejvm_execute!jvm_instruction = JVM_ILOAD_1jvm_instruction = JVM_IFEQ jvm_instruction = JVM_ILOAD_1Fig. 5: Excerpt of the generated Timed Automaton.Here, locations represent Java Bytecodes and thefiring of the outgoing edges initiates simulation ofthat Java Bytecode by consulting the respectiveTimed Automaton in the JVM NTA Layer (seeFig. 6).assembly_instruction = ASSEMBLY_ADD assembly_instruction = ASSEMBLY_ADCASSEMBLY_add_ID0_13assembly_instruction = ASSEMBLY_LPMASSEMBLY_adc_ID0_14ASSEMBLY_st_ID0_12 ASSEMBLY_lpm_ID0_15assembly_execute! assembly_execute!assembly_execute!Fig. 6: Excerpt of simulating a Java Bytecode.In turn, the Java Bytecode is simulated usingthe underlying Hardware NTA Layer (see Fig. 7).x == 1x <= 1execute!x = 0fetch?move(THIS, NEXT)x == waitx <= waitexecute?set_wait(),x = 0clear(THIS)Fig. 7: Pipeline fetch and execute stage, respectively.ResultsWe base the results on analysing two representa-tive examples of real-time systems written in Java:the Real-Time Sorting Machine (RTSM) and theMinepump control system. The systems have beenevaluated on the Java Optimized Processor (JOP),and an execution environment consisting of theHardware near Virtual Machine (HVM) on an AVRATmega2560 microcontroller. The results havebeen obtained on a system with an Intel Core i7-2620M @ 2.70GHz and 8 GB of memory. Theresults are shown in Table 1, 2, and 3.Execution Env. Clock Freq. SchedulableHVM + AVR 10 MHz XHVM + AVR 5 MHz ×JOP 2 MHz XJOP 1 MHz ×Table 1: Schedulability of the Minepump when varyingthe clock frequency.System Clock Freq. Idle UtilisationRTSM 100 MHz 4.0 ms 48.5 µs (1.2%)RTSM 60 MHz 4.0 ms 80.8 µs (2.0%)Minep. 100 MHz 2.0 ms 25.9 µs (1.3%)Minep. 10 MHz 11.8 ms 259.0 µs (2.1%)Table 2: Processor idle and processor utilisation timeswhen the system is schedulable on the JOP.RT Task WCRT Veri. TimePeriodic Task 1 62.3µs 60sPeriodic Task 2 18.4µs 10sSporadic Task 1 4.5µs 10sSporadic Task 2 4.5µs 25sTable 3: WCRT of the real-time tasks of the RTSM.Future WorkSupport other Analyses The Timed Automatamodel can be used for analysing other interestingproperties e.g. worst case blocking time.Statistical Model Checking[2] Can be used foranalysing systems for which probabilistic guaran-tees of temporal correctness are sufficient. Thetechnique can be used to avoid exhaustive explo-ration of the state-space of the model.Schedulability Abstractions[1] Decorate Java in-terfaces with abstract, behavioural descriptionsand generate Timed Automata accordingly.Case Studies We want to further evaluate the ap-plicability of TetaSARTS by using more complexreal-time systems, and possibly other variationsof the execution environment.Download TetaSARTShttp://people.cs.aau.dk/~luckow/tetasarts/References[1] T. Bøgholm, B. Thomsen, K. Larsen, and A. Mycroft. Schedu-lability analysis abstractions for safety critical java. 2012.[2] A. David, K. G. Larsen, A. Legay, M. Mikučionis, D. B. Poulsen,J. Van Vliet, and Z. Wang. Statistical model checking for net-works of priced timed automata. 2011.

Supporting Development of Energy-Optimised Java Real-Time Systems using TetaSARTS

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Supporting Development of Energy-Optimised Java Real-Time Systems using TetaSARTS

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