This paper discusses design considerations
for cascade Sigma-Delta Modulators (ΣΔMs)
included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural
simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC.Peer reviewe
