Adaptive filters, as part of digital signal systems, have been widely used, as well as in applications such as adaptive noise cancellation, adaptive beam forming, channel equalization, and system identification. However, its implementation takes a great deal and becomes a very important field in digital system world. When FPGA (Field Programmable Logic Array) grows in area and provides a lot of facilities to the designers, it becomes an important competitor in the signal processing market. In general FIR structure has been used more successfully than IIR structure in adaptive filters. However, when the adaptive FIR filter was made this required appropriate algorithm to update the filter’s coefficients. The algorithm used to update the filter coefficient is the Least Mean Square (LMS) algorithm which is known for its simplification, low computational complexity, and better performance in different running environments. When compared to other algorithms used for implementing adaptive filters the LMS algorithm is seen to perform very well in terms of the number of iterations required for convergence. This phenomenon can be achieved by a sufficient choice of bit length to represent the filter’s coefficients. This paper presents a lowcost and high performance programmable digital finite impulse response (FIR) filter. It follows the adaptive algorithm used for the development of the system. The architecture employs the computation sharing algorithm to reduce the computation complexity
