Transmitting images from earth observation satellites to ground is a major challenge, and a compression/encryption stage is actually mandatory. Development of hardware accelerators is highly recommended, both to relieve the software from such demanding task, and to improve performance, aiming at quasi-real-time data processing. To this end, we discuss the design, development, deployment and test of a FPGA-based accelerator, featuring a lossless and lossy (near-lossless) compression, including the data encryption too. Its architecture is well suited for different image types, including single- and multi-band optical and SAR images and can be fully run-time configurable. Measured performance showed a throughput of 10 Msamples/s, in agreement with related state-of-the-art works, focused on lossless compression only

Bianchi, Tiziano

Caon, Michele

Magli, Enrico

Martina, Maurizio

Ros, Paolo Motto

English

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

16 July 2022POLITECNICO DI TORINORepository ISTITUZIONALEHigh-Level Synthesis of a Single/Multi-Band Optical and SAR Image Compression and Encryption Hardware Accelerator/ Ros, Paolo Motto; Caon, Michele; Bianchi, Tiziano; Martina, Maurizio; Magli, Enrico. - ELETTRONICO. - (2021), pp.7835-7838. ((Intervento presentato al convegno 2021 IEEE International Geoscience and Remote Sensing SymposiumIGARSS tenutosi a Brussels, Belgium nel 11-16 July 2021 [10.1109/IGARSS47720.2021.9553765].OriginalHigh-Level Synthesis of a Single/Multi-Band Optical and SAR Image Compression and EncryptionHardware AcceleratorIEEE postprint/Author's Accepted ManuscriptPublisher:PublishedDOI:10.1109/IGARSS47720.2021.9553765Terms of use:openAccessPublisher copyright©2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in anycurrent or future media, including reprinting/republishing this material for advertising or promotional purposes, creatingnew collecting works, for resale or lists, or reuse of any copyrighted component of this work in other works.(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/2933980 since: 2021-11-11T12:10:49ZIEEEHIGH-LEVEL SYNTHESIS OF A SINGLE/MULTI-BAND OPTICAL AND SAR IMAGECOMPRESSION AND ENCRYPTION HARDWARE ACCELERATORPaolo Motto Ros, Michele Caon, Tiziano Bianchi, Maurizio Martina, Enrico MagliDipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino, Turin, ItalyABSTRACTTransmitting images from earth observation satellites toground is a major challenge, and a compression/encryptionstage is actually mandatory. Development of hardware accel-erators is highly recommended, both to relieve the softwarefrom such demanding task, and to improve performance,aiming at quasi-real-time data processing. To this end, wediscuss the design, development, deployment and test of aFPGA-based accelerator, featuring a lossless and lossy (near-lossless) compression, including the data encryption too. Itsarchitecture is well suited for different image types, includingsingle- and multi-band optical and SAR images and can befully run-time configurable. Measured performance showeda throughput of 10 Msamples/s, in agreement with relatedstate-of-the-art works, focused on lossless compression only.Index Terms— High-level synthesis, Hardware acceler-ator, FPGA, Optical and SAR imaging, lossy compression,CCSDS-123, Earth observation1. INTRODUCTIONSatellite Earth Observation (EO) is nowadays rapidly gain-ing traction and receiving significant ever increasing atten-tion thanks to emergent opportunities and challenges to beexploited, such as environment monitoring and civilian secu-rity. To this end, the latency in delivering EO products to theground surely is among the first key performance indicators.In [1] a latency below five minutes (below one minute in somescenarios) has been demonstrated to be an achievable goal.Among the products to be transmitted to the ground, (multi-band) optical and SAR images represent the most challengingones, due to their large size and the limited available commu-nication bandwidth. Therefore, a specific compression andencryption sub-system is needed.The aim of this work is to explore the feasibility, from thedesign to the deployment on the target platform, and initialperformance assessment of a hardware accelerator for com-pressing and encrypting single- and multi-band optical im-ages and SAR data. The implemented compression algo-rithm is derived from the CCSDS 123.0-B-2 recommendedstandard [2], with a more hardware-friendly pre-quantizationstage in front of the prediction loop rather than within the loopitself [3]. Encryption has been implemented by randomlyflipping the sign of the prediction residuals. To this end, apseudo-random generator based on the very efficient Keccakcryptographic functions [4] has been integrated.Considering the specifications of the whole data process-ing chain for next-generation EO satellites [1], a throughputof 10 Msamples/s has been deemed to be the target perfor-mance. This is in agreement with state-of-the-art relatedworks, where, for similar scenarios and designs, the reportedthroughput is in the range 10–15 Msamples/s [5, 6, 7]. Re-ported maximum throughput can be up to 150 Msamples/s [6],but it strongly depends on input/output data ordering, imple-mented features, configurability. Data ordering is a majorpoint, with Band-Interleaved by Pixel (BIP) images (whisk-broom scanners) enabling near one order of magnitude betterthroughput than Band-Interleaved by Line (BIL, push-broomsensors) or Band Sequential (BSQ) ones (everything elseequal) [6]. Similar discrepancies are reported for similar com-pression algorithms, e.g., Fast Lossless (FL), too [8, 7]. Thebottleneck is due to the weights update operations (strictlydepending on z): due to the different sample ordering, BILand BSQ architectures can not exploit pipeline optimizationsenabled by a BIP design. This is so critical to eventually posea constraint on the minimum allowed number of bands ininput image [9]. Other throughput bottlenecks are the quanti-zation stage (required in case of lossy compression) [3], andthe flexibility provided by enabling run-time configuration(e.g., in [9, 6] image size is fixed at synthesis time to optimizeresource usage and resulting performance).With respect to the related works, in our design we intro-duce a pre-quantization stage, enabling a lossless and lossy(or, better, near-lossless, i.e., bounding the maximum errorbetween the original and the reconstructed image) compres-sion in the same core, and the encryption support directlyintegrated in the compression process. All the parameters(including image size, number of bands, dynamic range,encryption key, and initialization vector) can be fully user-configurable at run-time. Performance will be presented withrespect to the quantization delta; differently from the relatedworks, both single and multi-band optical images, as well asraw SAR data, will be used as a part of the test/validationdataset. In particular, the need of processing optical imagesand raw SAR data, both “single-band arrays”, renders theoptimization opportunities in BIP architectures ineffective;therefore, an inherent BIL architecture (better suited for theinvolved sensors) will be developed.2. IMPLEMENTATIONThe resulting compression/encryption algorithm has beenfirst intensively and extensively tested, characterized, andvalidated through a reference implementation, written in thecommon C language. It has clearly shown to be a good can-didate for a full hardware implementation: considering thecomplexity of developing and validating a brand new imple-mentation (i.e., a completely new hardware implementationdesigned from scratch), a High-Level Synthesis (HLS) ap-proach has been preferred. Target platform features a XilinxZynq US+ ZU19EG, a Multiprocessor System-on-a-Chip(MPSoC) integrating a Processing System (PS) based on aquad-core ARM Cortex-A53 and a Programmable Logic (PL)based on the Xilinx UltraScale FPGA architecture in a singledevice.Fig. 1. Overview of the interfaces of the compression/encryp-tion hardware accelerator implemented on the target platform.The compression/encryption hardware accelerator, fromthe interface point of view, has a straightforward structure (seeFigure 1):• One (AXI4) master interface (128 bit data width) forreading/writing input/output images directly (acting asa DMA peripheral) from/to the external PS memory.• One slave (AXI4-Lite) interface to both setup/configurethe compression/encryption operations and to controlthe accelerator itself.• Few standard control signals: clock, reset, interrupt.From the software point of view, considering the cus-tom GNU/Linux OS available, the accelerator is viewed as aUserspace I/O (UIO) device, accessible through the standarddevice subsystem. The use of the hardware interrupt enablesa non-blocking management of the compression/encryptionimplemented in hardware.As a general rule, all the options of the reference imple-mentation have been kept configurable at run-time; option-ally, some of them can be fixed at synthesis time so to allowthe synthesis tools to further optimize the resulting architec-ture. Other parameters can only be set at synthesis time; theseare strictly related to hardware details, enabling to eventuallyimplement the designed solution on platforms other than theintended target one (e.g., significantly smaller FPGAs).Target clock has been set to 200 MHz. Other clockfrequencies have been investigated, including 100 MHz,250 MHz, and 300 MHz. While the last two could be aviable solution, they would offer marginal performance in-crease at the cost of more critical timings. At the same time,the upgrade from 100 MHz (initial target clock) to 200 MHzhas been deemed worthy from the performance perspectivewithout sacrificing tolerance on timings.Table 1. Resource utilization of the implemented compres-sion/encryption accelerator on the target ZU19EG platform,both at 200 MHz and 100 MHz clock frequency.Resource Available 200 MHz 100 MHzCLB 65340 32915 (50 %) 34487 (53 %)CLB LUT 522720 196087 (38 %) 202517 (39 %)CLB FF 1045440 149406 (14 %) 138202 (13 %)BRAM (tiles) 984 268 (27 %) 253 (26 %)DSP 1968 330 (17 %) 330 (17 %)Table 1 reports the resource occupation of the final designfirst synthesized and then integrated, synthesized, and imple-mented in the reference hardware design. Reported numbersare the final ones (not estimates) of the designed compres-sion/encryption accelerator only. Two cases have been im-plemented and tested, i.e., for two different clock frequen-cies, in order to explore different trade-off and then select themost suited. The source code and the configuration of the de-signed core is exactly the same in both cases. Considering theimplementation running at 200MHz (recommended), overallConfigurable Logic Blocks (CLBs) occupation shows a rel-ative large usage (near half of the available resources in thePL), but it still allows for integrating other (smaller) cores.The higher percentage of used CLB LUTs (38 %) with re-spect to the CLB FFs one (14 %) reflects the computationalcomplexity involved. This is confirmed by a significant usageof DSP blocks (17 %) and by a relative low usage of BlockRAMs (BRAMs, 27 %), especially considering that the corehas been configured to process images with a size up to 32768× 16384 and up to 8 bands (16 bit per pixel). By comparingthe two solutions, at 200 MHz and 100 MHz, we can see thatthey show similar numbers, although an increase in the over-all CLB occupation (+5 %) and a decrease in the BRAM one(-6 %). This is reflected in a different balance between CLBLUTs and CLB FFs, showing that, given the same designto be synthesized, targeting 100 MHz, allows, as expected,to “pack” more combinational logic between two successiveregister stages, thereby enabling shorter pipelines.3. RESULTSThe developed compression/encryption accelerator has beenthen deployed on the target platform, and by means of a testprogram (same interface as the reference one), finally vali-dated through the same test suite used all along the designstages. Runtime performance has been then measured, in soft-ware, taking into account the memory transfers (operated bythe core) too. All timings thus refer to elapsed time betweenthe start of the compression, with the entire image in the PSDDR external memory, and its end, with the entire encrypted(and compressed) image in the PS DDR memory again.The overall image test set is complete and sound, entirelyrepresenting the intended case scenarios. It can be dividedinto three main subsets: single-band optical (2 up to 13100×6000× 1), multi-band optical (96 up to 1119× 639× 5), andSAR data (4 up to 10254×3425×1) images. Due to the adap-tive nature of the compression/encryption algorithm, indeed,different kind of images could lead, e.g., to different through-puts. Main figure of merit for the assessment of the perfor-mance has been deemed to be the average time taken to com-press each pixel, measured in ns/pixel, which is independentof the image size. Performance results and comparison areshowed as a function of the compression quantization delta,as it is the main parameter controlling output data size (whichin turn impacts on the image transmission performance).Table 2. Median values (ns/pixel) of the compres-sion/encryption running in hardware (200 MHz clock).Lossless Quantization Optical Multi-band SAR rawdelta images images dataYes 0 125.6 123.1 128.6Near 1 108.1 112.2 126.1Near 2 103.8 105.8 124.5Near 4 100.4 99.8 121.3Near 8 98.3 97.7 115.2Near 16 98.4 97.4 102.0Near 32 97.1 97.2 100.7Figure 2 shows box and whiskers plot of all the resultssummarized, organized per quantization delta (as definedin [3]) and then per image set; Table 2 reports the medianvalues only. By comparing these values, we can further con-firm that the estimate of the compression and encryption ofan optical multi-band image can be in the same range ofa single-band optical one (relative difference in the rangebetween -2 % and 3.8 %), while the same operations on aSAR image can be slower (relative difference in the rangebetween 2.4 % and 20.9 %). Overall median processing timeis about 100 ns/pixel, resulting in a median throughput ofabout 10 Msamples/s (20 MB/s).Figure 3 shows the box and whiskers plots of the mea-sured performance with the accelerator at 200 MHz (recom-mended) and 100 MHz. It has to be remarked that perfor-mance is not halved, i.e., is not proportional to the ratio be-tween the two clocks. During the development stage this kindof “law of diminishing returns” was even more evident as theclock was further increased to 250 MHz or 300 MHz. Consid-ering the added difficulty to obtain then good timings results,made 200 MHz be the best trade-off between performance,resources occupation, and reliability.4. CONCLUSIONIn this work we presented the design and development of acompression and encryption hardware accelerator for (multi-band) optical images and SAR data. Leveraging a HLS designapproach, it has been successfully deployed on a Xilinx Zynqplatform, along with the full software stack. Measured perfor-mance on datasets comprising different image types and sizes,showed a throughput of about 10 Msamples/s (20 MB/s) withlossless and, most importantly, lossy (near-lossless) compres-sion options. The throughput is in agreement with relatedstate-of-the-art works, focused on lossless compression only,and demonstrates the viability of this approach for achievingvery low latency in the delivery of EO products to ground.5. ACKNOWLEDGEMENTSThis work has been supported by the project EO-ALERT, Eu-ropean Union’s Horizon 2020 research and innovation pro-gramme under grant agreement No 776311.6. REFERENCES[1] M. Kerr, S. Tonetti, S. Cornara, J. I. Bravo, R. Hinz,A. Latorre, F. Membibre, C. Solimini, S. Wiehle,H. Breit, B. Tings, O. Koudelka, F. Teschl, E. Magli,T. Bianchi, A. Migliorati, P. Motto Ros, M. Caon,R. Freddi, M. Benetti, F. Milani, G. Curci, S. Fraile,L. Garcia, C. Marcos, and A. Fiengo, “EO-ALERT: Anovel architecture for the next generation of earth obser-vation satellites supporting rapid civil alerts,” in 71st In-ternational Astronautical Congress (IAC), Oct. 2020.[2] The Consultive Committee for Space Data Sys-tems (CCSDS), Low-Complexity Lossless and Near-Lossless Multispectral and Hyperspectral Image Com-pression, vol. Blue Book, Feb. 2019, RecommendedStandard CCSDS 123.0-B-2.0 1 2 4 8 16 32delta100105110115120125130ns/pixel datasetopticaloptical-5bandssar-offsetFig. 2. Performance of the compression/encryption running in hardware (200 MHz clock).0 1 2 4 8 16 32delta100110120130140150ns/pixeldataset = optical0 1 2 4 8 16 32deltadataset = optical-5bands0 1 2 4 8 16 32deltadataset = sar-offsetoptimization200MHz100MHzFig. 3. Performance of the compression/encryption running in hardware at 200 MHz and 100 MHz.[3] D. Valsesia and E. Magli, “High-throughput onboard hy-perspectral image compression with ground-based cnn re-construction,” IEEE Transactions on Geoscience and Re-mote Sensing, vol. 57, no. 12, pp. 9544–9553, 2019.[4] A. Migliorati, T. Bianchi, and E. Magli, “Selective en-cryption in the CCSDS standard for lossless and near-lossless multispectral and hyperspectral image compres-sion,” in Image and Signal Processing for Remote Sens-ing XXVI, Lorenzo Bruzzone, Francesca Bovolo, andEmanuele Santi, Eds. International Society for Optics andPhotonics, 2020, vol. 11533, pp. 221–228, SPIE.[5] L. Santos, L. Berrojo, J. Moreno, J. F. López, andR. Sarmiento, “Multispectral and hyperspectral loss-less compressor for space applications (HyLoC): A low-complexity FPGA implementation of the CCSDS 123standard,” IEEE Journal of Selected Topics in AppliedEarth Observations and Remote Sensing, vol. 9, no. 2,pp. 757–770, 2016.[6] Y. Barrios, A. J. Sánchez, L. Santos, and R. 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High-Level Synthesis of a Single/Multi-Band Optical and SAR Image Compression and Encryption Hardware Accelerator

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High-Level Synthesis of a Single/Multi-Band Optical and SAR Image Compression and Encryption Hardware Accelerator

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