The paper focuses on the design and synthesis of hardware chip for Spatio and Viterbi encoding and decoding techniques. Both techniques are used for digital data encoding and decoding in transmitter and receiver respectively. These techniques are used for error control coding found in convolution codes. Spatio coding is also used to eliminate crosstalk among interconnect wires, thereby reducing delay. The encoded data is in packet form may be of 2018;N2019; bits. Data is decoded at different clock pluses at which it is encoded. A comparative analysis is done for hardware parameter, timing parameters and device utilization. Design is implemented in Xilinx 14.2 VHDL software, and functional simulation was carried out in Modelsim 10.1 b, student edition. Hardware parameters such as size cost and timings are extracted from the design code
