Resilient Cache Design for Mobile Processors in the Near-Threshold Regime

Abstract

Near-threshold computing embodies an intriguing choice for extending mobile processor battery life due to its high energy efficiency. However, process, voltage and temperature variations cause a significantly high failure rate of level 1 cache SRAM cells in the near-threshold regime compared to the super-threshold regime. In this work, we show that faulty cells in the near-threshold regime are highly clustered in certain regions of the cache. We then propose a low overhead technique to dynamically reduce the performance penalty due to process variations by exploiting the spatial congregation of faulty cells and application cache behaviors. Our experimental results demonstrate up to 78% reduction in performance loss over two state-of-art techniques