Design Characterization and Verification of Channel Bandwidth Selectivity and Linearity Performance of I/Q Baseband Receiver SoC

Abstract

This paper presents the methodologies used to characterize and verify critical parameters of a differential In-phase/Quadrature (I/Q) baseband channel of an integrated circuits system, consisting of amplifiers and filters in a single chip radio transceiver. It is a highly compact circuit of novel Software Defined Radio (SDR), System-on-Chip (SoC) to support Multi-Band and Multi-Mode operation. The architecture is designed to fulfill the critical requirements of very low power consumption, high linearity, very low noise floor, optimized chip size and high reliability for wideband radio networks transceiver applications. Integrating the entire wireless transceiver system into a single chip can greatly minimize its size, simplify assembly process, and decrease manufacturing costs. However, the characterization and verification processes of such customized SoC is very much daunting and time consuming. This paper discusses an industrial standard procedure to verify such requirements in complex design and development stages. In general, the required receiver baseband path consists of amplifiers and filters line-up to perform 75dB Inter-Modulation Distortion (IMD) suppression or blocking capability. Detailed parameters subjected to characterization are shown and verified to the specification of SDR transceiver SoC . The SoC architecture has low noise amplifier (LNA), local oscillator, down conversion mixer, post mixer amplifier, and baseband path. The baseband path includes several receiver components, such as amplifiers and low pass filters (LPFs) producing low BW selectivity errors, high linearity, and low baseband noise. Finally, the critical parameters of the amplifier and filter blocks are measured and verified to satisfy the required design specifications