In this paper, the ruggedness performance of GaN HEMT and SiC JFET devices in cascode configuration with a low voltage silicon power MOSFET has been evaluated experimentally. The impact of the bus voltage on the drain current and avalanche energy are investigated as well as the temperature sweep to enable analysis of the alternation of these parameters on the Unclamped Inductive Switching (UIS) ruggedness of cascode devices. The experimental measurements show that the GaN cascode devices have lower avalanche energy rating when compared with the closely rated SiC cascode devices just before the failure. SiC cascode devices can also withstand higher bus voltage in comparison to GaN cascode devices when under electrothermal stress by unclamped inductive switching. The analysis of transfer characteristics and leakage current of SiC JFET & GaN HEMT cascode structures following UIS stress have also been performed together with Computed Tomography (CT) Scan imaging to determine the per-area avalanche energy density
