Mackenzie Dover, Coinneach

Mount, Andrew R

Ross, Alan

Smith, Stewart

Terry, Jonathan G.

Walton, Anthony J.

English

This paper presents a previously documented full wafer test structure, designed to quantify the effect of seed layer thickness and conductivity on the plating uniformity of patterned electroplated structures. With magnetic films, non-magnetic seed layers need to be as thin as possible to minimise unwanted eddy currents. This paper uses the test structure to quantify the IR drop on the electroplated film and demonstrates how current distribution structures can be simply used to significantly improve wafer plating uniformity when using seed layer thicknesses of a few nanometers

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     Edinburgh Research Explorer                                      Application of a Test Structure for Minimising Seed LayerThickness of Electroplated Ferromagnetic FilmsCitation for published version:Ross, A, Mackenzie Dover, C, Smith, S, Terry, JG, Mount, AR & Walton, AJ 2022, Application of a TestStructure for Minimising Seed Layer Thickness of Electroplated Ferromagnetic Films. in 2022 IEEE 34thInternational Conference on Microelectronic Test Structures (ICMTS). IEEE, pp. 110-113, 34th IEEEInternational Conference on Microelectronic Test Structures, 21/03/22.https://doi.org/10.1109/ICMTS50340.2022.9898250Digital Object Identifier (DOI):10.1109/ICMTS50340.2022.9898250Link:Link to publication record in Edinburgh Research ExplorerDocument Version:Peer reviewed versionPublished In:2022 IEEE 34th International Conference on Microelectronic Test Structures (ICMTS)General rightsCopyright for the publications made accessible via the Edinburgh Research Explorer is retained by the author(s)and / or other copyright owners and it is a condition of accessing these publications that users recognise andabide by the legal requirements associated with these rights.Take down policyThe University of Edinburgh has made every reasonable effort to ensure that Edinburgh Research Explorercontent complies with UK legislation. If you believe that the public display of this file breaches copyright pleasecontact openaccess@ed.ac.uk providing details, and we will remove access to the work immediately andinvestigate your claim.Download date: 27. Oct. 2022Application of a Test Structure for Minimising SeedLayer Thickness of Electroplated FerromagneticFilmsAlan W.S. Ross1, Coinneach M. Dover1, Stewart Smith2, Jonathan G. Terry1,Andrew R. Mount3 and Anthony J. Walton11 School of Engineering, Institute for Integrated Micro and Nano Systems,The University of Edinburgh, Edinburgh, Scotland, UK. Email: Anthony.Walton@ed.ac.uk2 School of Engineering, Institute for Bioengineering, The University of Edinburgh,Edinburgh, Scotland, UK. Email: Stewart.Smith@ed.ac.uk, ORCID: 0000-0002-7004-92193 School of Chemistry The University of Edinburgh, Edinburgh, Scotland, UK. Email: a.mount@ed.ac.ukAbstract—This paper presents a previously documented fullwafer test structure, designed to quantify the effect of seed layerthickness and conductivity on the plating uniformity of patternedelectroplated structures. With magnetic films, non-magnetic seedlayers need to be as thin as possible to minimise unwanted eddycurrents. This paper uses the test structure to quantify the IRdrop on the electroplated film and demonstrates how currentdistribution structures can be simply used to significantly improvewafer plating uniformity when using seed layer thicknesses of afew nanometers.I. INTRODUCTIONThe electroplating method is perhaps the most widespreadtechnique in microelectronics and microsystems fabrication forthe production of thick (tens of µm) metallic films e.g. Cu andNiFe. This paper uses a previously reported test structure [1]to quantify the IR drop across a wafer when electroplatingon seed layers with a thickness of a few nanometres. Moreimportantly, it demonstrates how IR drops resulting from thinseed layers can be significantly reduced by using dummystructures as current shunts on the mask layout.II. BACKGROUNDThe electroplating process typically involves the blanketdeposition of a seed layer, upon which photoresist is coatedand patterned to define a mould for the subsequent bottom-upplating process [2], as shown in Figure 1.Once the electroplating has been completed, the photoresistis stripped, followed by the removal of the now exposed seedlayer, which was electrically connecting all of the electroplatedmetal structures. This latter step is routinely performed using awet-etch dip process. In many cases the seed and electroplatedfilm are the same metal and care is needed with dimensionalcontrol. Clearly a more ideal situation is to use a seed layerwith a good etch selectivity with respect to the electroplatedfilm [1] to minimise any undercut and preserve the dimensionsof the electroplated film. At the same time, for structures withFig. 1. Bottom up plating using a photoresist mask [1] (note. thicknesses notto scale).dimensions approaching the seed thickness any undercut canresult in the structure being released. Hence, in this situationthere is a real need to minimise seed layer thickness whilealso minimising IR voltage drop.For conducting films, e.g. Cu, the electrical characteristicsof the seed layer under the electroplated film are not of keyimportance. For example, a thin Ti adhesion layer under Cuactually marginally reduces track resitivity. This is not thecase for magnetic films. In this case there are conflictingrequirements; the seed layer should have a high conductivity,to minimise IR drop during plating, but a very high resistivity,to minimise eddy current losses.For magnetic films, the performance requirements dictateseed layer (e.g. Cu, Al) thickness to be as small as possibleto minimise the conductivity of the seed layer during deviceoperation. Clearly the increase in IR drop can be countered byusing additional higher conductive tracks strategically placedto help distribute the plating current.Typically, electroplating systems are set up to deliver uni-978-1-6654-8566-1/22/ $31.00 © 2022 IEEEform blanket depositions, which minimises any non-uniformityrelated to current crowding resulting from the pattern. In thisregime any IR drop across the wafer is rapidly reduced asthe plating proceeds to increase the effective thickness of theseed layer, and will have a negligible effect on uniformity andfinal thickness of the deposited films. However, for bottom-up plating this is not the case as the seed layer betweenstructures remains a high resistance path leading to high IRdrops. With current flow being pattern dependent this presentsa challenge when developing generic layouts for setting upplating systems.Figure 2 shows the mask layout of the test structure, whichhas been designed with radial symmetry. It is also designed sothat the resistance between any two adjacent electrodes will bethe same for uniformly deposited films. The semi-automateddesign software is detailed in reference [1].Fig. 2. Mask layout for the electroplating of the 150 mm wafer showing theposition of the O-ring and jig contacts [1].III. ASSUMPTIONSExtracting quantitative information from the proposed teststructure makes the following assumptions1) The seed layer is uniform.2) The electrode connecting the outer electrode to the waferjig is thick enough to ensure all the outer electrode ringis at the same potential.3) There is good contact in the wafer jig.4) Current flow is radial.5) The resistance of each seed layer ring is identical.6) The seed layer sheet resistance is ≫ than the electro-plated layer.Most of these conditions are met by the mask design and uni-formity deposition issues will be discussed in the measurementsection.IV. FABRICATIONFabrication of the test structures used standard processesfor depositing the adhesion and seed layers, and defining thearea for electroplating. There are many options for improvingthe thickness/conductivity of the outer electrode. Ideally itwould be good to use a conductor that is not attacked bythe electrolyte so O-ring leakage on the wafer holder is lessof an issue. In this paper e-beam evaporated Al was used inconjunction with a simple shadow mask. The same e-beamevaporation system was also used to deposit the adhesion andseed layers.V. MEASUREMENTSFigure 3 shows results from [1] of the measured radialthickness of the Ni electroplated electrodes on three differentthicknesses of Al/Ni seed layers with a total plating currentof 0.65 mA (Note: a single power supply was used, withthe wafer and thief currents [3] being individually recorded).Figure 4 shows this setup.The thickness measurements were made on the nine elec-troplated rings starting from the centre of the wafer (1) outto the edge (9). These results indicated that it is feasible toelectroplate on patterned moulds using very thin seed layers.However, it should be noted that the thickness (conductivity)of the seed layers significantly affects the plating rates andradial uniformity, especially for the 5/5 nm (Al/Ni) seed layercombination [1].Assuming electroplating is 100% efficient, the test structureenables the IR drop of the seed layer rings to be calculatedknowing the total electroplating current, and the thickness andarea of each of the metal rings being plated. Figure 5 showsthe calculated IR drops for the 5/5 nm wafer and it can beobserved that the voltage drop reduces towards the centre ofthe wafer as the electroplating current reduces. Note that thenumbering of the electrodes and resistors in this graph and inFig. 2 is reversed compared to the numbering of the thicknessmeasurements. This extraction of IR assumes the electrodesbeing plated are much more conductive than the seed layer andthe resistance between any two electrodes is independent ofposition of the probes on the electrodes. For the measurementsin Figure 3 it can be observed this is not the case and is onlyan approximation. This result was caused by uneven contactto the outer electrode, the O-ring leaking electrolyte whichattacks the electrode, and known non-uniform deposition ofthe e-beam seed layer. Addressing seed layer non-uniformityrequires access to a more modern sputter tool or an atomiclayer deposition system.The test structure provides the opportunity to more quan-titatively investigate the effect of adding current shunts todistribute current to reduce wafer IR voltage drops. Figure 6shows a simple cross design with Figure 7 presenting thedeposited thickness measurements along the horizontal andvertical radii. The improvement over the same measurementwithout the shunts is self-evident. Additional investigation isrequired to fully determine the reason for the variation in thetrend of the thickness at different positions on the wafer.(a)(b)(c)Fig. 3. Radial uniformity measurements for different seed layers (1-9 centre-east, 10-18 centre-west, 19-17 centre-south, 28-36 centre-north). (a) 5 nm Al/ 5 nm Ni, 0.068 A (b) for 10 nm Al / 10 nm Ni 0.212 A, (c) 50 nm Al / 50nm Ni, 0.155 A.Fig. 4. Wafer plating jigs, with (left) and without (right) a current thief [1]Fig. 5. IR drop on 150mm wafer (5nm Al / 5nm Ni seed)VI. DISCUSSION AND CONCLUSIONSA test structure has been presented, which has been specif-ically designed to quantify the IR drop across a wafer duringelectroplating in a more product independent manner.It has been demonstrated how this test structure can beused to evaluate the concept of dummy structures or currentshunts and their effectiveness in the distribution of currentsfor thin seed layers with sparse plating areas. The use ofsuch dummy structures to enable uniform plating of suchsparce patterns with thin seed layers is of particular importancewith magnetic films and the need to minimise eddy currents.What is clear is that the deposited film in the reported resultsis non-uniform, in spite of which, this test structure stillprovides an excellent vehicle to investigate the effectivenessFig. 6. 150 mm wafer with dummy current structures (5nm Al / 5nm Niseed).Fig. 7. Uniformity of deposition on 150 mm wafer with dummy currentstructuresof current shunts to reduce radial electroplating related non-uniformities. It confirms that 10 nm seed layers can be usedfor electroplating magnetic films with significantly lower eddycurrent losses.REFERENCES[1] C.M.M. Dover, A.W.S. Ross, S. Smith, J.G. Terry, A.R. Mountand A.J. Walton, “Test structures for seed layer optimisation ofelectroplated ferromagnetic films,” 2018 IEEE International Confer-ence on Microelectronic Test Structures (ICMTS), 2018, pp. 63-68,doi:10.1109/ICMTS.2018.8383766.[2] R. Walker, E. Sirotkin, J.G. Terry, S. Smith, M.P.Y. Desmul-liez and A.J. Walton, “Effect of seed layers on the performanceof planar spiral microinductors,” 2014 International Conference onMicroelectronic Test Structures (ICMTS), 2014, pp. 135-140, doi:10.1109/ICMTS.2014.6841481.[3] Ang, J, “Method for electroplating metal films including use a cathodering insulator ring and thief ring”, US Patent 574401

Application of a Test Structure for Minimising Seed Layer Thickness of Electroplated Ferromagnetic Films

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Application of a Test Structure for Minimising Seed Layer Thickness of Electroplated Ferromagnetic Films

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