This paper introduces a digitally performedcurrent mode and voltage control for the dc-dc step downconverter based on voltage to frequency converter where theaverage values of inductor current and output voltage areobtained. These current and voltage measurement arerealized by the voltage control oscillator (VCO) andcounters (digital integrator). Such an approach enables fulldigitalization of current and voltage control loops

Konjedic, Tine

Milanovic, Miro

Truntic, Mitja

English

CTU Open Journal Systems (Czech Technical University, Prague / České vysoké učení technické v Praze)

Transactions on Electrical Engineering, Vol. 1 (2012), No. 1                                                                                            1 ________________________________________________________________________________________________   Digital Current Mode Control for Buck-Converter Based on Average Inductor Current Measurement  Miro Milanovič1),  Mitja Truntič2), Tine Konjedic 3)  1) University of Maribor FERI, Maribor, Slovenia, milanovic@uni-mb.si 2) University of Maribor FERI, Maribor, Slovenia, mitja.truntic@uni-mb.si 3) University of Maribor FERI, Maribor, Slovenia, tine.konjedic@uni-mb.si  Abstract— This paper introduces a digitally performed current mode and voltage control for the dc-dc step down converter based on voltage to frequency converter where the average values of inductor current and output voltage are obtained. These current and voltage measurement are realized by the voltage control oscillator (VCO) and counters (digital integrator). Such an approach enables full digitalization of current and voltage control loops. Keywords—DC-DC converters, converter control, current control I.  INTRODUCTION Digitally controlled pulse-width modulation (PWM) converters have many potential advantages, including programmability, insensitivity to parameter variations, reduction of external passive components, as well as the potential to apply more advanced algorithms for the control and protection. When using microprocessors the computing capabilities are not fast enough to calculate the necessary time critical calculations for the control algorithm during the switch period. Later, advances in  digital technology prompted some research groups to use Field-Programmable Gate Array’s (FPGA’s) or Digital Signal Processors (DSP’s) [1], [2] and [3]. In the current mode, the switch or the inductor current is sensed within an inner loop and replaces the conventional saw-tooth waveform when generating the Pulse Width Modulation (PWM) function. Such algorithms were used within the domain of the analogue solution but recently, some algorithms were mainly developed based on an instantaneous current measurement and prediction strategy [4], [5]. According to digital approach in order to solve DC-DC converter control function it must be noted that the digital controller samples the sensed current at least twice in switching period and the actual trajectory of the inductor current is unknown to the controller. According to digital control approach the current must be sampled at least twice during the switching period in order to solve DC-DC converter control function whereas the actual trajectory of the inductor current is is unknown to the controller. Some research work was done in digitalization area where prediction method was used. The inductor current has been sampled at least twice, when the current was rising (within Ton interval) or falling (within Toff interval) as was discussed in [4]. By using such algorithm the peak or valley current-mode control could be applied.   This paper explores a current mode control for a dc-dc buck converter based on the average value of the inductor current measurement, by using a voltage-controlled oscillator   Figure 1.  (a) The buck converter schema - analog  architecture;  (b) The buck converter schema - current-mode analog  architecture;  (c) current modulator-analog solution; (d) current-modulator,  digital solution and digital counter for the inductor current measurement. The algorithm was investigated theoretically and verified by simulation and experimentation. II. PRINCIPLE OF OPERATION  The block diagram of a cascade controlled buck converter and analog current mode control schema is shown in Fig. 1 (a) and (b) respectively. The current reference iref is obtained as an output of the voltage controller. Better dynamics response can be achieved by the use of current-mode control schema. The conventional PI controller and the saw-tooth waveform generator (Fig. 1 (a)) which is used to generate the PWM signal is replaced with the inner current loop. Replacement of the inner current loop Fig. 1 (b) is done by the introduction of the switch (isw) or inductor current (iL) which is compared to the current reference signal. The resulting signal is led to the R-S flip-flop in order to generate the triggering pulse for the transistor (PWM signal). For the digital implementation the structure of Fig. 1 (b) cannot be directly used. The digitalization principles, which will be considered here, enable and/or provide the current information also during the sampling interval. The new digital principle of current   Transactions on Electrical Engineering, Vol. 1 (2012), No. 1                                                                                            2 ________________________________________________________________________________________________   - mode control is proposed in Fig. 1 (d).  Voltage-controlled oscillators (VCO) and digital counters were used instead of classical A/D converters. VCO is also known as voltage-frequency converters (u/f converter).  Such organized control of the buck converter is shown in Fig. 2.  Figure 2.  Current mode concept:(a) Ordinary PWM approach;  (b) Current-mode control replacing the classical PWM..  A. The current-mode control operation Referring to Fig 2, in steady state the current control function is started when the clock pulse (cl .) appears. For the sake of simplicity in the block schema only one counter is shown, but the actual signal (from u/f) is divided into two clock signals iL(f-on) and iL(f-off) for the two counters indicated in signal diagrams in Fig. 3. Both signals are led to the appropriate counters. Comparator resets the flip-flop if the sum of both counters contents meet reference current iref, represented by 16-bit digital numbers. The counter “integrates” the VCO pulses iL(f-off)  during the Toff  interval  simply by counting and as an output the IL(dig) signal is generated.  B. Current-measurement mathematical analysis The instantaneous VCO frequency of these pulses (fi) can be calculated from: ( ) 0i iLf ku t f= +     (1) where 0f  represents offset frequency, and k is the VCO constant (for chosen VCO, 0 23f = MHz and  15.6k = MHz/V). Voltage uiL appears on the VCO input after the inductor current was measured at the shunt resistor (Rsh) and amplified with the (Aβ) constant. It yields iL sh Lu A R iβ=     (2) where  ( ) max 1min 2;    when  ;    when  Li a t Tr OFFi ti a t Tr ON− == + =  (3) The current has a maximum indicated by imax and minimum indicated by imin (Fig. 3). Coefficients a1 and a2 depend on the circuit parameters (ud - uo)/L and -uo/L respectively. The new clock signal appears at the end of interval Toff   where the flip-flop is set and the Tr is switched ON. At the same time another counter also starts, which integrates the pulses of VCO  during the interval Ton. The reset signal appears on the R flip-flop input when the sum of both counters reach reference current, and Tr is switched OFF.  Figure 3.  The typical waveforms: iL-inductor current; iL(f-on)-VCO signal for inductor current when Tr is ON,  iL(f-off)-VCO signal for inductor current when Tr is OFF, IL(dig)-contets of counter (average inductor current);  cl-flip- flop clock signal; δ− PWM-triggering pulse.  Both counters must be reset to zero in order to start the  new current measurement. This procedure is repeated during the converter operation. The VCO generates an output signal iL(f-on) connected as a clock  signal  to  the  digital  counter. The same VCO output signal is connected inside the FPGA on the two counters. VCO frequency ( )i offf − changes during interval Toff as follows from (1), (2) and (3):  1 2i offf t− = Λ − Λ     (4) where 1 max 0shkA R i fβΛ = +  and 2 1shkA R aβΛ = and also VCO frequency changes during Ton: 1 2i onf t− = Γ + Γ     (5) where 1 min 0shkA R i fβΓ = +  and 2 2shkA R aβΓ = .  Equations (4) and (5) show how the instantaneous value of inductor current changes the VCO frequency. In order to evaluate the inductor current average value next formula must be used:  ( ) ( )( ) ( )( )2 20 01 20 1111 1t tL L it ts st ti off i ont tsI i t dt K f t dtT TK f t dt f t dtT − −= == +∫ ∫∫ ∫ (6) Transactions on Electrical Engineering, Vol. 1 (2012), No. 1                                                                                            3 ________________________________________________________________________________________________   where K1 is digital scaling factor.  Equation (6) is modified by using notations in Fig. (4) as follows: ( ) ( )0 012 21 2 1 22 2x yL si off i onI T f d f dKx yx y− −= τ τ + τ τ= Λ − Λ + Γ + Γ∫ ∫  (7)  Figure 4.  The waveforms: inside measurement circuit.  Figure 5.  Conceptual scheme of inductor current measurement. So at the end of integration process (end of interval Ts) inside of FPGA the average value of the inductor current is available as the state of  adder (refer Fig. 5). ( )1L soff on iLI T Z Z ZK= + =   (8) where  ( )21 2 2offZ x x= Λ − Λ  and ( )21 2 2onZ y y= Γ + Γ .  From (8) it can be evaluated the inductor current average value over the interval Ts, as follows ( )1L iLsKI ZT=  (9) C. Voltage-measurement mathematical analysis Referring to Fig 2, in steady state the voltage control function is started when the clock pulse (cl .) appears. The VCO converts voltage into frequency: ( )0 0u tf a u t f= +     (10) Where at is the measurement resistor attenuation, f0 is the VCO offset frequency and voltage u0(t) is represents by: ( )0 0u t U=      (11) The VCO is started with voltage to frequency conversion and generates at its output pulses indicated as u0(f) in Fig. 6. At the same time this VCO signal is counted by counter and at the end of Ts interval there is an “average” output voltage available as follows:  Figure 6.  The voltage measurement waveforms: u0-output voltage; u0(f)-VCO signal for output voltage, U0(dig)-contets of counter (average output voltage);  cl-flip- flop clock signal; δ− PWM-triggering pulse.  ( ) ( )1 20 020 01 t tut ts sKU u t dt f t dtT T= =∫ ∫   (12) where K2 is digital scaling factor. Equation (10) is modified by using notations in Fig. (6) as follows: ( )0 102xsuU T f d xK= τ τ = Π∫ ,  (13) and at the end of interval Ts inside of FPGA, the average value of the output voltage can be evaluated from (13) as follows: ( )10 0uKU ZT=   (14) where ( )21 2 2uZ x x= Π + Π  and represents the state of the counter connected to the VCO dedicated for voltage measurement and must be captured from counter for voltage control purposes at the end of interval Ts.   III. RESULTS AND DISCUSSION (SIMULATION AND EXPERIMENTATION) A. Simulation The current-mode control based on the proposed principle has been simulated with the use of the MATLAB-SIMULINK (Fig. 7). The current measurement was performed by using the u/f converter. The elements of Simpowersystem toolbox were used and also the whole measurement principle and controllers based on SIMULINK blocks was developed.  Transactions on Electrical Engineering, Vol. 1 (2012), No. 1                                                                                            4 ________________________________________________________________________________________________   It is prescribed that the switching frequency is fs = 25 kHz (Ts = 40 µs). The parameters used were: L = 270 µH, C = 100 µF, u0 = 5 V and ud = 12 V. Figs. 8 show the transient response when the output voltage was controlled during the load change from 6.8 Ω to 3.4 Ω , and vice-versa. The proposed algorithm was also verified by experiments. The experiment was set-up by the cascade control structure were the necessary current reference was calculated by the voltage controller.   Figure 7.  Simulation schema  Figure 8.  Input and output voltage and current waveforms: reference and output voltage uref and u0 respectively (uper diagrams)  and inductor current iL when load changed from 6.8Ω →3.4Ω → 6.8Ω. For the current and voltage measurements the u/f measurement principle was applied, as was outlined in the previous text. The voltage PI controller parameters were designed frequency domain by using the Bode diagrams. Small signal model based on state space averaging method were used as it is proposed in [6]. B. Experimental set-up Based on the above described principle of operation the experimental set-up with buck-converter circuit and appropriate FPGA unit was build (Fig. 9). As was claimed in the previous section it was necessary to carry out appropriate processing of the inductor current measured quantity with the aim that the u/f converter will operate in the right area. First of all, u/f converter output frequency starts to vary when its input voltage is greater than 0.7 V. When the measured and amplified signal of inductor current has less than (u(iL) < 0.7 V) the u/f converter oscillates with minimum oscillation frequency, whereby the information has been lost, and therefore additional adder circuit was added, which allowed the current measurement from 0 to 2 A (0 - 3 V). Fig. 10 shows the analogue part of inductor current measurement acquisition system. The current information is provided from shunt resistor and amplified by INA (IC1) circuit. Afterwards the uoffset is added to the information of the inductor current.  Figure 9.  Experimental set-up circuit.   Figure 10.  Analogue data aquizition measurement circuit for inductor current. When the inductor current information is obtained and appropriate processes are connected to the u/f converter (Fig. 11). The whole inductor current measurement “chain” was tested and calibrated as shown in Fig. 12. Yellow area indicates the input voltage range ( ) ( )0,  3 iLu V∈ . The u/f output frequency changes almost linearly as was presumed in (1). The K1 digital scaling factor defined in (9) is set as the ratio between the 3V maximum input u/f voltage range and the sum of the two counters. As followed from Fig. 5 for current measurement two counters inside the FPGA were used. The first one counts “the current” during the time period Toff and the second one during Ton. The meaning of constant K1 and K2 should be explained here. From Fig. 12 follows that the maximum frequency of u/f converter Transactions on Electrical Engineering, Vol. 1 (2012), No. 1                                                                                            5 ________________________________________________________________________________________________   is 140 MHz. So between two signals pulses indicated by cl. (Fig 3. and Fig. 6) can be counted 5600 (fvco/fPWM) of quanta. Constant K1 and K2 can be calculated by: 1 215600pwmvcofK K f= = =    (15) The voltage measurement was performed on the same way. Only one digital counter was used inside the FPGA because of almost completely flat voltage waveform.  Figure 11.  The schema of voltage to frequncy converter for inductor current measurement.   Figure 12.  The static characteristic of VCO.   Figure 13.  Analogue data aquizition measurement circuit for buck-converter output voltage.   Figure 14.  The schema of voltage to frequncy converter for output voltage measurement This counter is synchronized with the end of triggering pulse δ. The analogue acquisition part of voltage measurement circuit is shown in Fig. 13 and u/f schema is shown in Fig. 13 and VCO circuit in Fig. 14.  Figure 15.  The voltage and current waveform when load was changed from 6,8Ω → 3.4Ω → 6.8Ω  Figure 16.  The voltage and current waveform cut-off;  start-up voltage and current wave-form C. Results and discussion The current-mode control based on the proposed principle has been verified by experimentation. The current measurement was performed by using the u/f converter. The switching frequency is set to fs = 25 kHz (Ts= 40 µs) and the buck converter circuit parameters are chosen as was suggested in the simulation: L= 270 µH, C = 100 µF, u0 = 5 V and ud = 12 V. The experiment was set-up by the cascade control structure were the necessary current reference was calculated by the voltage controller. For the current and voltage measurements the u/f measurement principle was applied, as was outlined in the previous text. Fig. 15 shows the transient response when load was changed as indicated in the figure capture. The voltage reference was set to 5 V. Fig. 16 shows start-up response of buck-converter output voltage and inductor current. The average inductor current is limited to 1.5 A. Figs. 17 and 18 show close-up when the load has changed from 6,8 Ω → 3.4 Ω.  and 3.4 Ω → 6.8 Ω  respectively.  The voltage controller generates the current reference which changes from 0.75 A to 1.5 A and vice-versa. The voltage dynamic error was approximately 400± mV.  Transactions on Electrical Engineering, Vol. 1 (2012), No. 1                                                                                            6 ________________________________________________________________________________________________   IV. CONCLUSION The voltage and current control-mode control algorithm can be performed in a digital way as it is shown in this paper. The VCO based current and voltage measurements enable such approach.   Figure 17.  The voltage and current waveform cut-off;  when load was changed from 6,8 Ω → 3,4 Ω.  Figure 18.  The voltage and current waveform cut-off;  when load was changed from 3.4 Ω → 6.8 Ω. The algorithm is based on average current and voltage measurement by using the voltage to frequency conversion instead of conventional A/D converters. Both measurements were performed by using the VCO. Such an approach is suitable for the implementation of all algorithms in the FPGA circuit. It is, therefore, adequate for many industrial applications such as high power multi-phase DC-DC converters.  REFERENCES   [1] E. Vidal-Idiarte, L. Martnez-Salamero, F. Guinjoan, J. Calvente and S. Gomariz ,“Sliding and fuzzy control of a boost converter using an 8-bit microcontroller,”  IEE Proceedings-Electric Power applications, vol. 151, N 01, pp. 5-11,  Jan. 2004 [2] M. Milanovic, M. Truntic, P. Slibar and D. Dolinar, ‘Reconfigurable digital controller for a buck converter based on FPGA. Microelectron. Reliab., vol. 47, no. 1, pp. 150-154, January, 2007 [3] B. J. Patella, A. Prodic, A. Zirger and D. Maksimovic, “High-frequency digital pwm controller IC for dc-dc converters,” IEEE Transactions on Power Electronics, vol.18, no 1, pp. 438-446, January 2003. [4] J. A. Gow, C. D. Manning, “Novel fast-acting predictive current mode controller for power electronic converters,” IEE Proceedings-Electric Power applications, vol 148, N 2, pp.133-139, March 2001. [5] M. Truntič, M. Milanovič, E. Vidal-Idiarte, C. Carrejo, C. Alonso,  “Digital current mode and voltage control for the DC-DC step-up converter based on the FPGA technology”. V: 14th International Power Electronics and Motion Control Conference,  EPE-PEMC 2010.  [6] R.D. Middlebrook, S. Cuk  “A General Unified Approach to Modeling Switching Power Stages.” IEEE Power Electronics Specialist Conference-PESC77, pp. 36-37, May. 1977. 

Digital Current Mode Control for Buck-Converter Based on Average Inductor Current Measurement

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Digital Current Mode Control for Buck-Converter Based on Average Inductor Current Measurement

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