This paper presents a Power Hardware-in-the-Loop (PHIL) emulation test bench for emulating highly utilized perma-nent magnet synchronous machines (PMSM). The output stage of the PHIL is a Cascaded H-bridge based Parallel Hybrid Converter (PHC) with a 17-level output voltage and an effective switching frequency of 1 MHz. The nonlinear machine is emu-lated with a sampling frequency of 5 MHz and is implemented on a field programmable gate array (FPGA) using Matlab/Simulink\u27s HDL Coder. For this purpose, the time-discretized model equations of a PMSM and the PHIL test bench are derived and their mapping into an HDL code-generable and fully fixed-point transformed model in Simulink is described. To enable the high model sampling rate of 5 MHz, it is optimized for a low clock cycle count and the nonlinear relations between the machine currents and flux linkages are stored in lookup tables (LUT). The measurements are carried out in steady-state operation as well as for highly dynamic current and rotor speed steps. They demonstrate the excellent performance of the presented PHIL test bench, which even perfectly reproduces the current ripple of the modeled PMSM
