The objective of this study is to design a field-programmable gate array (FPGA) implementation of a
cognitive radar (CRr) target recognition system for electronic warfare applications. This thesis expands on
the closed-loop adaptive matched waveform transmission technique called probability of weighted energy
(PWE). This work also investigates the feasibility of applying the PWE technique in a functional digital
hardware realization. Initially, a PWE Monte Carlo simulation model is developed in the Verilog hardware
description language that is simulated in the Xilinx Vivado environment. The Verilog module components
developed in the Monte Carlo model are then incorporated into a CRr target recognition system experiment
utilizing the Xilinx VCU118 Evaluation Board. The VCU118 features the Virtex UltraScale+
high-performance FPGA to accomplish CRr adaptive waveform generation and transmission, digital signal
processing requirements, and target classification. The Rohde & Schwarz SMW200A Vector Signal
Generator and FSW Signal & Spectrum Analyzer function as the radar system transmitter and receiver,
respectively, while the FPGA implementation enables the closed feedback loop used by the CRr.Lieutenant Commander, United States NavyApproved for public release; distribution is unlimited
