Cyber-Physical-Social Systems, commercial enterprises, and social networking use data centers to store, process, and 

distribute massive amounts of data. A data center serves as the foundation for all of these endeavors. The data center's workload 

and power consumption are increasing rapidly due to the demand for remote data services. Mechanical refrigeration and terminal 

cooling are the most critical components for most cooling systems. There is a way to transfer heat from the data center to the 

outside environment, but it's a complicated process. Air cooling systems and technology are most useful for room cooling and 

rack-level cooling. Because of their superior cooling performance and higher energy efficiency, air cooling has attracted more 

attention than water cooling in most existing data centers. The chillers and fans consume the most power of all the cooling 

equipment in the system. These methods can be divided into mechanism-based methods and data-driven methods for energy 

management of the cooling system. Operation management of cooling equipment is proposed to reduce power consumption, 

mainly using predictive model control and reinforcement learning-based methods. An overview of the data center's cooling system 

is presented in this paper, which focuses on the most common cooling solutions, power consumption modeling methods, and 

optimization control strategies, among others. In addition, the data center's cooling system is described as a current and future 

issue

Ali, Khairul Fahmi

Baharudin, N.

Gerijih, Debie Devisser

Hazrati, K. Z.

Qibtiah, Raja Mariatul

Razali, Nizamuddin

UTHM Institutional Repository

VOL. X, NO. X, XXXXXXXX ARPN Journal of Engineering and Applied Sciences  ©2006-2013 Asian Research Publishing Network (ARPN). All rights reserved. ISSN 1819-6608   www.arpnjournals.com  INVESTIGATION OF THRESHOLD VOLTAGE AND TRANSCONDUCTANCE VARIATIONS IN PMOS  Siti Hajar Marni Hasbulah, Rahmat Sanudin Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn Malaysia (UTHM), 86400 Parit Raja, Johor, Malaysia  E-Mail: rahmats@uthm.edu.my   ABSTRACT Scaling process of MOSFET has yielded great benefit in term of processor technology evolution. However, it is worth to note that the scaling process also affects the electrical parameters as well. It is expected that as MOSFET gradually scaled into the submicron regime, the variation of electrical parameters due to scaling becomes more apparent. The study is carried out through simulation work of 45 nm p-type MOSFET (PMOS) using a commercial device simulator. This tool is used as a medium to observe changes in threshold voltage (VTH) and transconductance (gm). Changes of both parameters are investigated against three factors; oxide thickness (tox), doping concentration of dopant in substrate and doping energy. Observation in simulation results suggest that increment in both tox and doping energy  increases VTH and reduces gm. In contrast, increment in doping concentration of dopant improves gm and trims VTH. Analysis of results deduces that the variations of both VTH and gm against those three factors are related to number of free carriers during device operation.   Keywords: threshold voltage  transconductance  submicron PMOS   INTRODUCTION  The scaling process has contributed to significant changes in device dimension of MOSFET. To date, the scaling process helps integrated circuit industry to sustain the Moore’s Law. A compromise design is essential to accommodate both high performance and low power logic (Zeitzoff and Chung, 2005) as the transistor technology advances. High switching speed and low leakage current are required to achieve the compromised design. The scaling process also heavily dependent on velocity and mobility of carriers to ensure a proper operation (Khakifirooz and Antoniadis, 2008).  High leakage current and electron tunnelling mechanism have been identified as major issue when transistor is scaled  (Zietzoff and Chung, 2002), (Ning, 2007). Parasitic resistance due to source or drain extension also another issue in transistor scaling (Plummer, 2000). Furthermore, variation in fabrication process also affects the performance of scaled transistor (Saha, 2014). High bias potential also leads to other shortcoming such as hot electrons and oxide reliability (Ning, 2007). A proper bias in accordance to scaled device dimension is important to preserve reliability (Bohr, 2007). In spite of numerous challenge in MOSFET scaling, it is expected that the scaling process will continue. Innovations in channel material selection (Antoniadis et al., 2006), (Thompson et al., 2005) and device structure (Majumdar et al., 2014), (Xin et al., 2008) are among novel approaches that will extend the scaling process. Using metal as source.drain terminals is also being considered since it could reduce electron tunnelling and sheet resistance (Larson and Snyder, 2006), (Zietzoff and Chung, 2002). Another approach is to consider variants of MOSFET such as junction FET (Jackson et al., 2009) as a potential candidate of transistor in submicron regime. The main objective of this work is to investigate the variations of VTH and gm of PMOS in the submicron scale. The investigation is made against three factors, which are oxide thickness (t ), doping concentration of dopant in substrate and doping energy of dopant. The investigation is made through device simulation using Sentaurus TCAD.  DEVICE SIMULATION  Figure 1 exhibits the flow of device simulation carried out in this work. The work flow involves five components in Sentaurus TCAD which are Sentaurus Workbench (SWB), Ligament, Sentaurus Device (SDevice), Tecplot and Inspect. Firstly, the device input parameter was set in the SWB such as the gate length. Each node of input parameters could be run independently to obtain specific output files. During simulation, each node status would be represented with a unique colour. For example, a blue node represents a running simulation and an amber node represents a completed simulation. In general, the SWB acts as a tool to give an overview of the whole process in Sentaurus TCAD. Nevertheless, the individual process must be defined before it appears on the SWB interface.  Next, the changes in oxide thickness were simulated in Ligament. This was done by specifying the length of oxidation process in Ligament. At the end of the process simulation, a series of oxidation thickness was obtained to be used in the next step of simulation. The variability of oxide thickness was then used to examine the change in the VTH. The following steps were to obtain the device doping profile in Tecplot. The doping profile was generated according to the doping concentration specified in SWB. The doping profile was obtained once the process simulation in Ligament has completed. It means that any changes in process simulation defined in Ligament will affect the doping profile. As shown in Figure 2, two input files were required in Tecplot which were <filename>.cmd and <filename>.tdr. Next, SDevice was used to extract output data of device operation such as current and voltage of interest. In addition, this tool also helped to determine the final solution of all structure variables. Finally, the electrical characteristic was extracted in visual mode using Inspect. VOL. X, NO. X, XXXXXXXX ARPN Journal of Engineering and  ©2006-2013 As The drain-to-source current (IDS) was one of the main output parameter viewed in Inspect. Two input files wein this simulation, namely <filename>.cmd<filename>.plt. Figure 3 shows the pre-process in Inspect before the output parameters are extracted.   StartSpecifying input parameters in SWBFabrication process simulation in LigamentDevice doping profile plot in TecplotExtracting output data in SDevicePlotting of electrical characteristic in InspectEnd Repeat process for n times. Have reach the nth process?YesNoFigure 1: Work flow of device simulation Figure 2: Pre-process of Tecplot simulation  filename_fps.cmd SProcessfilename_fps.tdr Tecplot Obtain device doping profile Structure Editor Applied Sciences ian Research Publishing Network (ARPN). All rights reserved. ISSN re required  and     Figure 3: Pre-process of Inspect simulation RESULTS AND DISCUSSION  A structure of 45 nm PMOS is obtained through fabrication process simulation in Ligament. Tecplot SV tool is used to display the device corresponding doping concentration The gate length is 44.47 nm as measured in the Tecplot SV. Figure 4: Device structure of 45nm P The oxide thickness shows linear relationship both the VTH and gm. As shown increases with respect to increment of the oxide thickness. Negative values of voltage indicate the operation of PMOS, which requires negative gate voltage to turn on the device.An inversion layer will be created when inversion layer, in turn, will aid the creation of channel just beneath the oxide layer to allow current flow between source and drain terminals. Therefore, a thinner oxide layer will require less VG to create channel and implies less VHowever, tox has opposite effect on gmThe changing trend implies that a required to obtain the same amount of will require a higher potential to be applied on to allow current conduction in PMOSchange in VG is needed to obtain the same lower tox. This explains the inverse proportionalthe tox and gm. The second factor being investigated is the effect of doping concentration of dopant in substrate towards Vand gm. The doping concentration exhibits an inverse proportionality with VTH as illustrated words, as the doping concentration increases, the becomes smaller or less negative.related to number of free carriers being created in the substrate. As the doping concentration is increased, so does the number of electrons. This will lead to creation a similar  filename_des.cmd  SDevice Plot the electrical characteristic     1819-6608   structure with the as shown in Figure 4.   MOS with in Figure 5, the VTH  VG is applied. The TH.  as shown in Figure 6. larger VG change is ID. Increasing the tox gate terminal . This causes a higher ID compared to ity between TH in Figure 7. In other VTH  This relationship is  filename.plt  Inspect VOL. X, NO. X, XXXXXXXX ARPN Journal of Engineering and Applied Sciences  ©2006-2013 Asian Research Publishing Network (ARPN). All rights reserved. ISSN 1819-6608  number of holes just beneath the oxide layer when VG is applied. A low VG is enough to create channel under the oxide layer due to high number of holes available for conduction. Therefore, as the doping concentration is increased, a higher number of holes will be available and a lower potential threshold is imposed for conduction. In Figure 8, it is observed that the doping concentration of dopant in the substrate has an exponential relationship with gm. This trend can be seen when the doping concentration is changed from 1010 cm-3 to 1011 cm-3, there is a significant change in gm. It implies that at high doping concentration of dopant, a small change in VDS results in large change of ID. This observation shares the same argument as in the case of VTH variation. As the dopant in substrate increases, a higher number of holes are created. When there are huge number of free carriers flow between the electrodes, a high current is created. This explains a big change in current with a small variation in applied VG as the doping concentration increases.  Finally, the variations of VTH and gm are being investigated against doping energy. As shown in Figure 9, VTH increases as the doping energy is increased. In general, doping energy is related to the depth of implanted dopants in the substrate. It means a high doping energy created a deep dopant implantation. It also implies that any free carriers available are placed much further away from the oxide layer. When VG is applied, these free carriers are also further away from channel that conducts ID. Therefore, a higher threshold potential is being imposed to turn the device into conduction mode. This observation explains the reason VTH is getting larger as the doping enegy increases. The same argument can also be used to explain the relationship between gm and doping energy. As illustrated in Figure 10, as the doping energy is increased,  gm reduces that implies a lower ratio of ID to VDS. Higher doping energy means the dopant is implanted much further in the substrate. Therefore, lower number of free carriers present during conduction that leads to low current. Any change in current will require a larger change in VDS, due to limited free carriers in the channel. In other words, gm reduces as less free carriers are available.   Figure 5: Change of VTH with respect to oxide thickness   Figure 6: Change of gm with respect to tox   Figure 7: Change of VTH with respect to impurity doping concentration in substrate   Figure 8: Change of gm with respect to impurity doping concentration in substrate   Figure 9: Change of VTH with respect to doping energy  -570-560-550-540-530-520-5102 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6Threshold voltage, VTH(mV)Oxide thickness, tox (nm)181920212223242 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6Transconductance, gm (mA/V)Oxide thickness, tox (nm)-518-517-516-515-514-5131.00E+09 1.00E+10 1.00E+11Threshold voltage, VTH(mV)Halo dose (cm-3)23.023.223.423.623.824.024.224.41.00E+09 1.00E+10 1.00E+11Transconductance, gm(mA/V)Halo dose (cm-3)-516.0-515.5-515.0-514.5-514.02 3 4 5 6 7 8Threshold voltage, VTH(mV)Halo energy (keV)VOL. X, NO. X, XXXXXXXX ARPN Journal of Engineering and Applied Sciences  ©2006-2013 Asian Research Publishing Network (ARPN). All rights reserved. ISSN 1819-6608   Figure 10: Change of gm with respect to doping energy  CONCLUSION  The scaling process of MOSFET is no doubt has yielded a significant evolution in integrated circuit technology. The transistor size reduces in several order and thus higher transistor count present in the integrated circuit. The processor, in turn, could provide more functionality as desired in the mass market.  Nevertheless, there are other changes in the scaling process apart from the device dimension. The variation of electrical paramenters are also important as the MOSFET enters the submicron regime. Therefore, this study is carried out to investigate the effect of scaling process on PMOS of 45 nm technology. The investigation is narrowed down to two electrical parameters, which are VTH and gm. There are three factors being investigated that may affect the values of VTH and gm; tox, doping concentration of dopant in substrate and doping energy of dopant. Simulation results show that both oxide thickness and doping energy has the same effect on VTH and gm. However, the doping concentration has opposite effect on VTH and gm compared to the other two factors. The difference of effect among the three factors lies in the presence of free carriers in the channel. Increment in the doping concentration promotes higher number of free carriers, and thus improves the gm and reduces VTH. In contrast, increment in both oxide thickness and doping energy suppresses the number of free carriers. This leads to less available free carriers that flow in the channel, which increases VTH and reduces gm.  Analysis of observation in this work gives a perspective of VTH and gm variations in PMOS. The three factors investigated in this study could help in optimising those factors to obtain the best ID. In addition, the analysis also emphasis the importance of the availability of free carriers in device operation.     REFERENCES Antoniadis, D. A., Aberg, I., Ni Chleirigh, C., Nayfeh, O. M., Khakifirooz, A. and Hoyt, J. L. (2006). Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations. IBM Journal of Research and Development 50(4.5): pp. 363-376.  Bohr, M. (2007). A 30 Year Retrospective on Dennard's MOSFET Scaling Paper. IEEE Solid-State Circuits Society Newsletter 12(1): pp. 11-13.  Jackson, J. B., Kapoor, D. and Miller, M. S. (2009). Junction Field Effect Transistors for Nanoelectronics. IEEE Transactions on Nanotechnology 8(6): pp. 749-757.  Khakifirooz, A. and Antoniadis, D. A. (2008). MOSFET Performance Scaling - Part I: Historical Trends. IEEE Transactions on Electron Devices 55(6): pp. 1391-1400.  Larson, J. M. and Snyder, J. P. (2006). Overview and status of metal S/D Schottky-barrier MOSFET technology. IEEE Transactions on Electron Devices 53(5): pp. 1048-1058.  Majumdar, K., Hobbs, C. and Kirsch, P. D. (2014). Benchmarking Transition Metal Dichalcogenide MOSFET in the Ultimate Physical Scaling Limit. IEEE Electron Device Letters 35(3): pp. 402-404.  Ning, T. H. (2007). A perspective on the theory of MOSFET scaling and its impact. IEEE Solid-State Circuits Society Newsletter 12(1): pp. 27-30.  Plummer, J. D. (2000). Silicon MOSFETs (conventional and non-traditional) at the scaling limit. 58th Device Research Conference pp. 3-6.  Saha, S. K. (2014). Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design. IEEE Access 2: pp. 104-115.  Thompson, S. E., Chau, R. S., Ghani, T., Mistry, K., Tyagi, S. and Bohr, M. T. (2005). In search of "Forever," continued transistor scaling one new material at a time. IEEE Transactions on Semiconductor Manufacturing 18(1): pp. 26-36.  Xin, S., Qiang, L., Moroz, V., Takeuchi, H., Gebara, G., Wetzel, J., Shuji, I., Changhwan, S. and Tsu-Jae King, L. (2008). Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap. IEEE Electron Device Letters 29(5): pp. 491-493.  Zeitzoff, P. M. and Chung, J. E. (2005). A perspective from the 2003 ITRS: MOSFET scaling trends, challenges, and potential solutions. IEEE Circuits and Devices Magazine 21(1): pp. 4-15.  Zietzoff, P. M. and Chung, J. E. (2002). Weighing in on logic scaling trends. IEEE Circuits and Devices Magazine 18(2): pp. 18-27.   23.524.024.52 3 4 5 6 7 8Transconductance, gm (mA/V)Halo energy (keV)

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