Atomistic to Circuit Level Modeling of Defective Doped SWCNTs with Contacts for On-Chip Interconnect Application

Abstract

Carbon nanotubes (CNTs) due to their high electrical/thermal conductivity, high ampacity, high tolerance to electro-migration [1] and small dimensions make them an ideal candidate for future on-chip interconnects [2]. Fabricating the CNTs, random chirality and some defects are introduced which can degrade the CNT electrical properties [3]. Additionally, the contact resistance between metal and CNT presents additional parasitics that impose restraints on the electron transport. Electrical models of CNT for interconnect application were developed several years ago [4-5]. In this paper, we explored on doped and defective single-wall CNTs (SWCNT (24,0)) including contact resistance as important physical parameters to assess the performance of fabricated SWCNTs realistically for back-end-of-line (BEOL) on-chip interconnects on VLSI circuit application