Performance of CMOS technology has been affected in nanosystems due to power dissipation, area, and reliability functionalities. A research initiative which investigates other possible systems with related capacities is QCA. In this paper, QCA nanotechnology was used to create a 1-bit comparator. These circuits are easy to create and do not require any crossovers. The proposed design is extremely efficient in terms of area, cell count, quantum cost and delay, which improves the performance in the range of 74.81%&nbsp;to 99.87%&nbsp; in terms of quantum cost. As a result, proposed designs are often found in various digital logics that require a small amount of space and low power consumption

Balaji, M.

Neelima, K.

V. Satyanarayana

English

International Journal of Engineering and Applied Physics

      103   Journal homepage: https://ijeap.org/      Optimal of 1-bit Comparator design and Energy Estimation using Quantum Dot Cellular Automata   V. Satyanarayana1, M. Balaji2, K. Neelima3  1M. Tech Scholar, Department of ECE, Sree Vidyanikethan Engineering College, Tirupati-517102. 2Assistant Professor, Department of ECE, Sree Vidyanikethan Engineering College, Tirupati-517102. 3Assistant Professor, Department of ECE, Sree Vidyanikethan Engineering College, Tirupati-517102.  Article Info  ABSTRACT   Received Mar 16, 2021 Revised Apr 14, 2021 Accepted Apr 22, 2021                Performance of CMOS technology has been affected in nanosystems due to power dissipation, area, and reliability functionalities. A research initiative which investigates other possible systems with related capacities is QCA. In this paper, QCA nanotechnology was used to create a 1-bit comparator. These circuits are easy to create and do not require any crossovers. The proposed design is extremely efficient in expressions of delay, cell count, area and quantum cost, which improves the performance within the range of 74.81% to 99.87% in terms of quantum cost. As a result, proposed designs are often found in various digital logics that require a small amount of space and low power consumption.  Keywords: Quantum dots  Cellular Automata  Comparator  Quantum cells  Edge computing This is an open access article under the CC BY license.  Corresponding Author: V. Satyanarayana,   Sree Vidyanikethan Engineering College, Tirupati-517507. Email: satyab.tech4@gmail.com   1. INTRODUCTION   The reliability of efficient transistor Semiconductor devices has strengthened the driving force behind the semiconductor industry's accelerated growth, chip density, lower power dissipation, and faster integrated circuit switching speeds. The quantum effect is significant in the operation of transistors in the deep nanometer environment. Other aspects with deep nanometer transistor circuit architecture include high energy consumption, power losses, and electron leakage [1-3]. It includes present and prospective application of digital systems; developing nanotechnologies are an exciting investment opportunity [2, 5, 6]. QCA is a fast-evolving technology for computational logic designs as well as solutions to CMOS in nanosystem issues [4, 7]. Since QCA can be built using molecules, its scalability is much preferable than that of silicon-based transistor scaling for CMOS.  A. QCA Nanotechnology         Nanotechnology based on QCA is one of the most efficient technologies being explored and researched by researchers. In 1993, C. S. Lend [1] was the first to suggest the concept of QCA. In order for the measurement and transformation process [4,7] the structure between cell charges is required and QCA is included in the cell concept. The elimination of cell contact wires or interconnection is another benefit of QCA electronic circuit design. There are four quantum dots or wells in each cell as shown in figure 1. In International Journal of Engineering and Applied Physics (IJEAP)Vol. 1, No. 2, May 2021, pp. 103~110  ISSN: 2737-8071Article history:   ISSN:2737-8071 Int J Eng & App Phy, Vol. 1, No. 2, May 2021: 103-110 104 this process, only two electrons are limited. Quantum tunnel junctions separate these quantum dots. The electron flow is caused by coulombic interaction between the cells. Electrons only arise at antipodal sites, ie. diagonally, due to coulombic repulsion, resulting in minimal repulsion. These electron residing positions eventually lead to the binary ‘0' and binary ‘1' polarisation states. The polarisation states of QCA cells are represented in Figure 2. In QCA [3, 8], energy dissipation is negligible during propagation and state transition, resulting in a low energy dissipation as compared to CMOS technology.   Figure 1. Schematic of QCA Cell. Figure 2. Binary QCA Cells.  B. QCA in Clocking        In addition, QCA circuit has four phases, each of which has a 90 degree differential between the circuit and only two clocking states: 'LOW' and 'HIGH.' The quantum tunnelling of electrons to other points in an input phase of a clock at certain stages by raising or lowering the barrier potential. Pipelining is a phenomenon that allows data to be transmitted. Switch, release, relax, and hold  are the four steps of this clocking. Since the QCA cells are unpolarized at first, they have a low potential.    Figure 3. Different clock phases in QCA.        During the switch cycle, the polarisation of a QCA cell is largely determined by the polarisation of adjacent cells, and the potential vitality of the electrons rises exponentially. Furthermore, no state change happens when the electron exceeds its full potential viability at the end of the switch stage. Cells maintain their previous state throughout the keep process, and their potential viability remains high. The electrons potential energy continues to decrease during the release and relaxation phase, gradually leading to null polarisation [4, 6, 7]. Figure 3 shows different clock stages.  C. QCA with Crossovers In circuit design, QCA wires crossover is usually used for simpler designs. Two forms of crossovers have been found in QCA. They are coplanar and multilayer crossovers. To crossover the wires, coplanar crossover is carried out in a single plane using direct and rotated cells is as shown in fig. 4, since there is no interaction between the cells or the use of alternative clock zones for crossovers. The other is a multilayer crossover, as Int J Eng& App Phy ISSN: 2737-8071   Optimal of 1-bit Comparator Design and Energy Estimation using QCA (V. Satyanarayana) 105 shown in figure. 5, which has more than one layer. Although multilayer crossover is more difficult to design than coplanar crossover, it is preferred because it reduces the number of cells and circuit area [1]. However, coplanar is preferred in terms of fabrication possibility.       Figure 4. QCA crossovers (a) with rotated cells, (b) with clock0 and clock2, (c) with clock1 and clock3.  Figure 5. QCA with multilayer crossover.  2. 1-BIT COMPARATOR         Figure 6. Logic diagram for a one-bit Comparator.     Binary comparators are used for optical comparators. Binary bits are measured by the 1-bit comparator to decide if one is greater and equal or less. Logic diagram of a one-bit comparator shows above.                                                                (2)                                        Here Y1, Y2 and Y3 are output equations. This one-bit comparator logic circuit appears in figure. 6 and the Truth Table is also shown in below.    ISSN:2737-8071 Int J Eng & App Phy, Vol. 1, No. 2, May 2021: 103-110 106                                                Table I. Truthtable for 1-bit comparator.  A. Literature Review    To analysis the various 1-bit comparators proposed in QCA, a  literature review was conducted.  A few designs that have been proposed are seen below figures. Other architectures build the comparators with reversible gates[2-6], but they use a multilayer or rotating cell solution with a very high cell count[4]. The conceptual designs are configured with only majority gates, but this usually leads to use the more no. of fixed cells of polarization which is inefficient from a design technology [4,5]. Figure 8 hires 87 cells to play the role of a 1-bit comparator. Figure 9 shows a multilayer architecture with fewer fixed polarization cells to achieve the desired goal with cell count of 73 cells and less number of cells. Many researchers implemented QCA comparator circuits earlier. In Ref[1] a coplanar QCA Comparator Circuit with 0.182 μm2 and 117 cells was constructed, as shown in Figure.7. A single-bit comparator was proposed in Ref. [2]. A multi-component structure with a 0.11μm2 and 87 QCA cells as shown in figure.8 will be required for this QCA comparator circuit. In Ref[3] a multi-layered QCA Comparator Circuit with 0.06 μm2 and 73 cells was constructed, as shown in figure.9.  Figure 7. 1-bit Comparator with 117 cells.  Int J Eng& App Phy ISSN: 2737-8071   Optimal of 1-bit Comparator Design and Energy Estimation using QCA (V. Satyanarayana) 107 Figure 8. 1-bit Comparator with 87 cells.   Figure 9. 1-bit Comparator with 73 cells.  B. Existing Design      A few 1-bit comparator designs are shown in figures 10,11, but the majority of these have a large area of cells and cell count. Various concept crossovers are also used in these designs. Moreover, the circuits latency is higher, leading to a higher quantum cost. Figure 10 shows a one-bit comparator with no crossover based on these conditions. The simulation results from the QCA Designer 2.0.3 tool, as seen in figure.12, can be used to check the design's effectiveness.  Figure 10. QCA Schematic Design-1 for 1-bit Comparator with 55 cells.  Figure 11. QCA Schematic Design-2 for 1-bit Comparator with 42 cells.     ISSN:2737-8071 Int J Eng & App Phy, Vol. 1, No. 2, May 2021: 103-110 108       There are 55 cells in the design, with a total area of cell is 0.0669 μm2. The XOR gate, which has only 42 cells and area of cell is 0.0407 μm2, was optimised to produce another architecture, as seen in fig. 10.  C. Proposed Design      The 1-bitcomparator design in fig.10 has a large cell area and cell count. In addition, the circuits' latency is higher, resulting in a higher quantum cost. This paper proposes a new 1-bit comparator without using crossovers as seen in fig.12. The simulation results from the QCA Creator v2.0.3 tool can be used to verify design's accuracy, as seen in figure.13.     Figure 12. QCA Schematic for 31 cells 1-bit Comparator.            The proposed schematic design has 31cells with the total area of  cell is 0.03μm2.   D. COMPARISON TABLE  E.  ENERGY CALCULATION USING QDE   If qca cells are separated for each clock cycle, they form a "bath" of energy, as described in qde. ebath is the total amount of energy transmitted to the qca'bath.' As a result, the sum of all ebath energies will be used to calculate total energy dissipation. The 3 main components of energy dissipation are eck, eev, and eio. eck is used to transfer energy to clocks, eev is used to transfer energy to the atmosphere, and eio is used to transfer energy to neighbouringqca cells. It's worth noting that ebath = eev, and this is a contradiction. The equation is eio = eout, where ein is the amount of energy entering the cell and eout is the amount of energy exiting the cell.There may be an error in the measurement of electricity, which can be expressed as err = eev(eck + eio). If the error is negative, the energy has been converted from the three components previously discussed. Average loop energy dissipation is 1.50e-003e ev, with minute error -1.48e-004e, while the 1.65e-002e-bit comparators are used with a negligible error of -1.63e-003ee ev and with total energy. The qde tool was used to calculate the energy dissipation of each coordinate.  Int J Eng& App Phy ISSN: 2737-8071   Optimal of 1-bit Comparator Design and Energy Estimation using QCA (V. Satyanarayana) 109   3.  RESULT  Figure 13. Waveform  simulation  for  the QCA 1-bit comparator 4.   CONCLUSION       According to the result  the comparator design is proficient in terms of  delay, area, quantum cost, cell count andit achieves performance of 72.91% to 99.87% over current proposed design, there are many designs to consider in expressions of quantum cost. As a result, the proposed design is used in a variety of technology with negligible space and low power consumption.  REFERENCES [1] A. N. Bahar and M D. Abdullah-Al-Shafi , “Optimized  design        and   performance  analysis  of  novel comparator and   full  adder      in  nanoscale,”  Cogent Engineering, vol. 3,  pp. 1-14, 2016.    [2] S. Waheed, N. Islam,  &   R. Akter, “Implementation of  reversible   logic gate in  quantum   dot  cellular   automata,” International      Journal  of  Computer  Applciations, vol. 109, pp. 41-44, 2017.  [3] S Kumari, Gupta S. H    and B. Ghosh, “Quantum dot cellular    automata magnitude comparators,” in Proc. of IEEE         International Conference on   Electronic Devices and Solid     State Circuits (EDSSC),  2012,  p. 1-2. [4] X. Yin-shui      and      Q. Ke-ming. “     Quantum       Dots      cellular automata      comparator”.       In     7 th     International      Conference on     ASIC,   ASICON    2007.,    Page(s) 1297-1300.    ISSN:2737-8071 Int J Eng & App Phy, Vol. 1, No. 2, May 2021: 103-110 110 [5] M. R. Garg,  B. Krishan,   A  Literature Review  on  Quantum    Dots, International Journal of  Advanced  Research    in    Electrical,    Electronics and  Instrumentation Engineering,  4 (2015). 7857‐7862. [6] Vikramkumar P, Sridharan K.  Design of   Arithmetic Circuits in   Quantum Dot Cellular Automata     Nanotechnology.  Switzerland:  Springer    International Publishing; 2015.    DOI:10.1007/978-3-319-16688-9 [7] QCA Designer-E (2017) https://github.com/FSillT/QCA Designer Accessed 12 Mar 2019. [8] S. Farrokhi,  K. Navi ,  N. Bagherzadeh, M. Hossein Moaiyeri      and  S. Angizi, “ Designing  quantum-dot cellular automata     counters with  energy   consumption  analysis”, Microprocessors       and  Microsystems, vol. 39, no. 7, (2015), pp. 512-520.  BIOGRAPHIES OF AUTHORS      V. Satyanarayana M.Tech Scholar, Department of ECE,  Sree Vidyanikethan Engineering College, Tirupati – 517102 satyab.tech4@gmail.com      M. Balaji Assistant Professor, Department of ECE,  Sree Vidyanikethan Engineering College, Tirupati – 517102 balajichaitra3@gmail.com       K. Neelima Assistant Professor, Department of ECE,  Sree Vidyanikethan Engineering College, Tirupati – 517102 neelumtech17@gmail.com    

Optimal of 1-bit Comparator design and Energy Estimation using Quantum Dot Cellular Automata

International Journal of Engineering and Applied Physic

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Optimal of 1-bit Comparator design and Energy Estimation using Quantum Dot Cellular Automata

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