Conductive lithographic films (CLFs) have been developed primarily as substitutes for resin/laminate boards, which share properties with the metallisation patterns used in planar microwave integrated circuits (MICs). The authors examine the microwave properties of the films and show that, although the losses are greater, they have potential as an alternative to the traditional manufacturing process of MICs

Evans, PSA

Harrison, DJ

Ramsey, BJ

Shepherd, PR

Electronics Letters

English

Brunel University Research Archive

into the pure CUT, that is, there was no additional circuit. The second and third rows, ‘D+pMOS’ and ‘PMOS’, show simulation results when using a diode and a PMOS of the same size as the proposed sensor, and when using a PMOS one-quarter the size of M1 as the I-V translator, respectively. The last row, ‘proposed’, shows the results for the proposed sensor, which reduces the volt- age drop at the VDD terminal of the CUT. It also performs rela- tively accurate measurement for a small current (i.e. relative error for 100kR fault resistance was 3.5%). Although the PMOS scheme for the I-V translator showed good performance concerning accu- rate measurement of a small current, it is difficult to apply the translator because it produces a small voltage drop and has a small noise margin. Table 1: Summary of IDDQ sensors Fault resistance (R,) for CUT lO0kQ D+pMOS 43.310.52 3 15.310.59 736.910.64 47.810.06 330.210.40 677.510.87 Proposed 46.610.19 3 18.610.54 742.810.61 CUT only 48.41 - 361.31 - 822.51 - [pA]/voltage drop at N1 M Fig. 3 shows simulated waveforms for the proposed sensor. The fault in the CUT was excited at two intervals: from 50 to lOOns and from 200 to 25011s. The output of the sensor produced a high voltage at both these intervals. The line of Inv(TouJ in the Figures shows the output of an inverter fed by To,,. The propagation delay times of lnv(Tou,) were 23.811s for R, = 100kQ and 3.3ns for R, = l0R. Thus the fault detection time of the sensor becomes slower as the fault current decreases. Conclusions: A sensor with low voltage drop and accurate current measurement is proposed for IDDQ testing. Simulation results showed that this sensor satisfied the primary objective, but was not fast enough in the case of smaller fault current. This will be a subject of future research. 0 IEE 1997 Electronics Letters Online No: 19970334 Y. Miura (Department of Electronics and Information Engineering, Tokyo Metropolitan University, 1-1 Minami-Osawa, Hachioji, Tokyo 192-03, Japan) E-mail: miura@eei.metro-u.ac.jp 28 January 1997 References 1 SODEN, J.M., HAWKINS, C.F ,  GULATI, R.K., and MAO, w.: ‘IDDQ testing: A review’, JETTA, 1992, 3, (4), pp. 291-303 2 MALY, W., and NIGH, P.: ‘Built-in current testing - Feasibility study’. Proc. Int. Conf. Circuit-Aided Design, 1988, pp. 340-343 3 MIURA, Y., and KINOSHITA, K.: ‘Circuit design for built-in current testing’. Proc. Int. Test Conf, 1992, pp. 873-881 4 SHEN, T.-L., DALY, J.c., and LO, J.-c.: ‘A 2-11s detecting time, 2 p n  CMOS built-in current sensing circuit’, IEEE J. Solid-State Circuits, 1993, 28, (l), pp. 12-77 TANG, J.-J., LEE, K.-J., and LIU, B.-D : ‘A practical current sensing technique for IDDQ testing’, ZEEE Trans. VLSI Systems, 1995, 3, (2), pp. 302-310 6 ATHAN, s P., LANDIS, D.L., and AL-ARIAN, s.A.: ‘A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs’. Proc. VLSI Test Symp., 1996, pp. 118-123 7 LU, C.-W., LEE, c L., and CHEN, ].-E.: ‘A fast and sensitive built-in current sensor for IDDQ testing’. Proc. IDDQ Workshop, 1996, pp. 56-58 5 ELECTRONICS LETTERS 13th March 1997 Vol. 33 Lithographic technology for microwave integrated circuits P.R. Shepherd, P.S.A. Evans, B.J. Ramsey and D.J. Harrison Indexing terms: Microwave integrated circuits, Lithography Conductive lithographic f h s  (CLFs) have been developed primarily as substitutes for resinilaminate boards, which share properties with the metallisation patterns used in planar microwave integrated circuits (MICs). The authors examine the microwave properties of the films and show that, although the losses are greater, they have potential as an alternative to the traditional manufacturing process of MICs. Introduction: Conductive lithographic films (CLFs) are fabricated on paper substrates using a specially formulated silver-loaded ink and a standard lithographic printing process [l]. The resulting ink films consists of a thin layer ( - 3 p )  of silver particles suspended in an organic resin binder. The pattern can be overprinted, with excellent registration, to achieve thicker layers if required. CLFs were developed primarily as an alternative to traditional residlam- inate boards for low frequency applications and have already been successfully tested in a range of telephone plant, microprocessor and security tagging applications. The structure of the printed films is however very similar to the metallisations used in planar microwave integrated circuits (MICs). The use of CLFs in MICs or other planar structures has two main perceived advantages. First, owing to the simple printing process, it is likely to provide a cheaper manufacturing process for bulk applications. Secondly, owing to their flexible nature, CLF substrates can be readily bonded to curved substrates, whereas curved circuits are difficult to achieve in the standard MIC proc- ess. This could have applications in certain antenna structures (e.g. helical antennas or dipoles on co-axial feeds). The perceived disad- vantages are that there is still a requirement for a base substrate onto which the paper is bonded. This is because the very thin paper substrate would require extremely narrow metallisation pat- terns to achieve suitable characteristic impedances. The second perceived disadvantage is in the loss of the films being higher than traditional MIC metallisations (e.g. copper). Conductive lithographic films: In the CLF fabrication process, a conductive ink is deposited by a standard lithographic printing press to directly form circuit patterns on the substrate material. The ink developed for the CLF printing process consists of sus- pension of metallic silver particles in an organic resin. Although this resin is non-conductive, it acts as a vehicle for the conductive particles and partly determines the mechanical properties of the ink. The current ink formulation contains a high proportion (-SO% wlw) of silver flake with a mean particle size of 2 1 pn. The substrate material consists of a paper or polymer base, whose sur- face properties permit the adhesion of the ink, and allows contact between adjacent ink particles. Gloss art paper, and coated poly- ethylene have been used in printing trials. Work to date has clearly demonstrated that standard litho- graphic printing technology can be adapted to electronic circuit fabrication. Printing trials have yielded ink films deposited onto paper substrates which have acceptable electrical characteristics. Typical CLF sheet resistivities approach those encountered in thick-film circuit practice, and CLF substrates have been assem- bled into a range of functional electronic systems. Interest in the microwave properties of CLFs has arisen as a consequence of the similarity of deposited films to the metallisa- tion patterns employed in MICs. In particular, the films exhibit a high degree of electrical conductivity, a surface roughness equiva- lent to the mean ink particle size (1 ,urn), and, in consequence of the lithographic printing process, excellent dimensional control and registration of the deposited ink films. Microwave test circuits: Two basic circuit forms were generated for assessment of the CLFs, nominally 50R through lines of dif- ferent lengths and a ring resonator structure. The same photolith- ographic artwork was used to construct the through lines on No. 6 483 standard copper-clad Duroid samples as well as the CLF patterns, for direct comparison of the characteristics. For measurement purposes the paper CLF substrate was bonded onto a Duroid substrate which had had the top copper layer removed, but retained the copper ground plane. Clearly the additional paper thickness and higher dielectric constant of this layer will mean that the CLF line will no longer be 50Q, but part of this work was to assess the change in effective dielectric con- stant from the pure Duroid line. The samples were measured using an HP8510B vector network analyser. Ths  was calibrated in 3.5” coax, so the effect of the microstrip launchers is included in the measured results. By having identical structures, but of different lengths, and assuming the launcher characteristics are reasonably repeatable, it is assumed that these effects can be accounted for in the assessment [2]. Effec- tively we can use the copper-clad Duroid as a calibration standard to assess the loss characteristics of the CLF lines. 0 -1 -2 cg -3 v- N vr - L  -5 - 6  0 5 10 15 2 0  frequency, GH z Fig. 1 Measured S,, for 2in through lines (i) copper (ii) cured CLF (iii) uncured CLF Results and discussion: Fig. 1 shows the measured S,, for the through line on a 2 in long substrate. The top trace shows the nor- mal copper clad Duroid and shows an increasing loss to -2dB at 20GHz. This is almost entirely due to the launchers as the expected loss in such structures increases to around O.ldB at 20GHz. The second two traces are for the identical structure in CLF. The ‘uncured’ measurement is the result taken shortly after the substrate was printed, while the ‘cured’ trace is taken about 10 days later. This illustrates a trend that is already known in that the conductive properties on the CLF alter with time, taking around a week to settle at room temperature. DC resistance meas- urements taken on samples at about the same time as the micro- wave measurements indicated a change in sheet resistance from 0.9 to 0.6UU. This increase in DC conductivity is reflected in a decrease in microwave loss of -0.3dB across the band. -1 % r- -2 N t I 0 5 10 15 frequency, GHz 164)12) Fig. 2 S,, of CLF lines referenced to copper lines (i) l in line (ii) 2in line The ripple in these plots is due to the relatively poor return loss of the microstrip launchers. The reflections which are set up inter- fere with the forward power wave. The constructive and destruc- tive interference depends on the relative phases of the signals, this in turn depends on the electrical length of the line which is a func- tion of frequency. Hence the ripple effect with frequency. The shape of the ripple in the two measurements is similar, indicating a reasonable repeatability of the mounting fEture. A similar meas- urement was carried out using a lin substrate. The CLF lines again show greater loss, the curing process reducing the loss by -0.1-0.2dB. This is entirely consistent with the results from the 2in substrate where the line was twice the length. Referencing the CLF results to the copper results helps eliminate the launcher rip- ple and gives a good estimate of the excess loss of the CLF line. Fig. 2 shows these results for the two lengths of line, which indi- cates that the loss per inch of the CLF microstrip line increases almost linearly from -0.5dB per inch at DC to -1.8dB per inch at 18GHi. It may be possible to improve these figures, as previous print runs have had sheet resistances as low as 0.3UU. Through measurements were also made on the ring resonator structure and the resonant frequencies determined. From these, the effective dielectric constant (EDC) was calculated to be 2.15 for the CLFDuroid structure. This compares with a figure of 1.89 for a line of the same width on the Duroid substrate. This increase is due to the higher dielectric constant of the paper layer and is consistent with a measured value of 7.5 for the paper at DC. The higher EDC results in a lower value of characteristic impedance for the CLF structure (to -47Q) and an electrical length dfferent from the copper line. This is why the ripple is not completely elim- inated in Fig. 2, where the referencing procedure relies on the same electrical length and characteristic impedance for both lines. Conclusions: A new lithographic process (CLF) has been described which is suitable for application to MICs. CLF microstrip struc- tures have been constructed and measured to assess their useful- ness at microwave frequencies. The loss of these lines has been estimated at 2dB per inch at 2OGH2, which represents a value at the poorest end of the spread of film conductivities which have been measured. While this loss is reasonably high, it would not preclude their use in MICs where the circuits are small or loss is not too important. The perceived advantages of low bulk cost and/or use in curved circuit structures would make the use of CLFs at microwave frequencies a useful alternative for many cir- cuits. The measurements carried out on the ring resonators have shown that the effective dielectric constant is increased due to the extra paper dielectric layer. This alters the characteristic imped- ance and electrical length of the lines, but this can be taken into account in the circuit design. Acknowledgment: The authors acknowledge the co-operation of Gwent Electronic Materials (Pontypool, Gwent), for their collabo- ration in aspects of this work. This work was partly funded by the EPSRC Electronic Product Design and Manufacture Initiative. 0 IEE 1997 Electronics Letters Online No: 19970360 P.R. Shepherd (School of Electronic and Electrical Engineering, University of Bath, Claverton Down, Bath, United Kingdom) P.S.A. Evans, B.J. Ramsey and D.J. Harrison (Department of Design, Brunel University, Runnymede Campus, Englefield Green, Egham, Surrey, United Kingdom) 6 January 1997 References 1 HARRISON, D., BILLETT, E ,  and BILLINGSLEY, J.: ‘Novel circuit fabrication techniques for reduced environmental impact’. Int. Conf. Clean Electronic Products and Technology, Edinburgh, UK, 9-11 October 1995 2 SHEPHERD, P.R., EVANS, P.s.A., RAMSEY, B J , and HARRISON, D.J.: ‘Assessment of conductive lithographic films for microwave applications’. Proc. 25th Automated RF and Microwave Measurement Society Meeting, Bath, UK, 1996 484 ELECTRONICS LETTERS 13th March 1997 Vol. 33 No. 6 

Assessment of conductive lithographic films for microwave applications’.

Novel circuit fabrication techniques for reduced environmental impact’.

Lithographic technology for microwave integrated circuits

Lithographic technology for microwave integrated circuits

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