Power dissipation besides chip area is still one main optimization issue
in high performance CMOS design. Regarding high throughput building blocks
for digital signal processing architectures
which are optimized down to the physical
level a complementary two-phase clocking scheme (CTPC) is often
advantageous concerning ATE-efficiency.
The clock
system dissipates a significant part of overall power up to more than 50%
in some applications.
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One efficient power saving strategy for
CTPC signal generation is the charge balancing technique.
To achieve high efficiency with this approach
a careful optimization of timing relations within the control
is inevitable.
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However, as in modern CMOS processes device variations
increase,
timing relations between
sensitive control signals
can be affected seriously.
In order to compensate for the influence of global and local variations in this
work, an adaptive control system for charge balancing in a CTPC generator
is presented. An adjustment for the degree of charge recycling is performed
in each clock cycle.
In the case of insufficient recycling
the delay elements which define duration and timing position of
the recycling pulse are corrected by switchable timing units.
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In a benchmark with the conventional clock generation system,
a power reduction gain
of up to 24.7% could be achieved. This means saving in power
of more than 12% for a complete number-crunching building block
