Abstract: In this paper anew boost topology is proposed. The circuit is similar with two parallel boost dc-to-dc converters, but the two inductors are charged in parallel and release energy in series, thus enhancing the voltage boost ratio. After a short analysis of the circuit, a comparative study with other classic boost converter (single boost and twocascade) is presented. The simulation results show a net improvement of the boost ratio for the new proposed topology

Nicolae, Dan-Valentin

Van Rensburg, J. F. J.

English

University of Johannesburg Institutional Repository

   A NEW DC-DC DOUBLE-BOOST TOPOLOGY FOR  ENHANCING THE VOLTAGE RATIO  DV Nicolae* and JFJ van Rensburg** *Tshwane University of Technology, Electrical Engineering Department, P. Bag X680, Pretoria, 0001, South Africa **Vaal University of Technology, Vanderbijlpark, South Africa danaurel@yebo.co.za; hannesvr@vut.ac.za      ABSTRACT In this paper anew boost topology is proposed. The circuit is similar with two parallel boost dc-to-dc converters, but the two inductors are charged in parallel and release energy in series, thus enhancing the voltage boost ratio. After a short analysis of the circuit, a comparative study with other classic boost converter (single boost and two-cascade) is presented. The simulation results show a net improvement of the boost ratio for the new proposed topology.  KEY WORDS DC-DC conversion, boost converter, modelling, simulation    1.  Introduction  An increased boost factor suits the many emerging applications in the automotive industry, telecommunications industry, and IT industry as well as power generation via fuel cells, photovoltaic arrays and wind turbines [1-8].  The basic boost topology does not provide a high boost factor.  This has led to many proposed topologies such as the tapped-inductor boost, cascaded boost and interleaved boost converters [5-8].  This paper introduces another variation which provides a higher boost factor and also provides for the possibility to gear up or down thus extending the control range. Although control methods such as fuzzy logic [11], sliding mode control [14] and others [10, 12, and 14] are available, a simple PI controller is used to verify the proposed double -boost topology.   2.  Proposed Model  Fig. 1 shows the proposed topology. The inductors L1 & L2 have the same values, the diodes D1-D3 are the same type and the same assumption was for the transistors (Q1 & Q2). Each inductor has its own switch and thus is similar with the paralleling of two single/classic converters.             Fig. 1 Proposed Model   2.1 Equivalent Diagram in ON State  Let us firstly consider ideal components. When the transistors Q1 & Q2 are in ON state, the proposed topology transfers energy from the dc source (Vb) into the inductors L1 & L2 as can be seen in Fig.2, where i1 is the current through inductor/transistor 1, i2 is the current through inductor/transistor 2, io is the output current through load RL and C is the smoothing capacitor.           Fig.2 Equivalent diagram for Q1 = Q2 = ON  2.2 Equivalent Diagram in OFF State   During the OFF state, the two inductors are connected in series, as shown in the equivalent diagram (Fig. 3).  + Vb L1 L2 Q2 Q1 D1 D2 D3 C RL ● ● ● ● ● ● ● ● ● ● D1 L L + Vb ● ● C Io Q1 Q2 i2 i1 RL ● ● ● ● Vo ● ● 625-047 174            Fig.3 Equivalent diagram for Q1 = Q2 = OFF  2.3 Boost Factor The switching frequency is high enough so the differential equations governing the circuit could be linearized. For the charging interval (Q1 = Q2 = ON), the voltage across each inductor is Vb and the currents i1(t) and i2(t) could be written as: ( ) ( ) ( )1 2 0b LVi t i t t IL= = +  (1) where IL(0) is the initial current through inductor at t = 0. When the transistors are turned OFF at t = δT (δ being the duty cycle), the voltage across inductors is Vo – Vb and the current iL(t) is: ( ) ( ) ( )2b oL LV Vi t t T I TLδ δ−= − +  (2) Evaluating eq. (1) at t = δT and (2) at t = T, the system becomes: ( ) ( ) ( ) ( )1 2 0bL LVI T i t T i t T T ILδ δ δ δ= = = = = +  (3) ( ) ( ) ( ) ( )02b oL L LV VI i t T T T I TLδ δ−= = = − +  (4) The converter is design to operate in continuous mode and IL(0) = IL(δT). From the system of (2) and (3) the boost factor Mp for the proposed circuit can be deducted: 21opbVMV δ= =− (5) As can be noticed, the boost factor of the proposed topology is double as regarded to the simple boost converter.  3. Boost Comparison  In order to enhance the advantage of the proposed boost topology, a boost factor comparison with a single and two-cascaded converter is necessary. This should be done taking in consideration the real values of components.   3.1 Simple-boost converter As presented in [9], the boost factor (Ms) depends on inductor resistance (rL) as: ( )( )1/ 11LsLrMRδδ = − + −   (6) When taking in consideration voltage drop across the diode (Vd) and transistor resistance in saturation (rdson), the boost factor becomes: ( )( )1/ 11swon dsL br VMR Vδδδ = − + − −   (7)  3.2 Two-cascaded boost converter When two identical simple converters are connected in cascade (Fig. 4), the boost factor (Mc) is affected by the capacitor (C) in the first unit and switching synchronization. Eq. (8) shows the boost factor for the cascade.          Fig.4 Double cascade boost converter  ( )( )( )2 / 1/ 11 1s L swon dcL L bT r r VMR C R Vδ δδδ δ    + = − − + −    − −         (8) 3.3 Proposed double-boost converter For this topology, all the real parameters should be taken in consideration at once. As can be noticed, the currents through inductors are slightly uneven, but for a good approximation they still can be considered equal. Then the boost factor could be written as:  ( )( )22 / 11L swon dL br r VMR Vδδδ += − + − −   (9) It can be seen that the inductance resistor and voltage across transistor resistor in ON state are considered with unity factor because the charging is parallel and independent one of each other, while the diode voltage drop has a coefficient two because they both are in series when the energy is transferred to the output.    Vo ● iL ● ● + Vb VL1 D3 ● D2 VL2 iC C RIo ● ● D1 D2 L L C C Q1 Q2 RL Vb + 1754. Control System  For this study, a simple IP controller has been used, as shown in Fig. 5.             Fig.5 Double-boost converter, control system  In the steady state, the power balance between input and output can be written as: ( )21b s o o odV I V V IC dt= ⋅ +  (10) Based on this dynamic equation, majority of authors have proposed a classic PI regulator. But the closed-loop transfer function of this type of regulator has two zeros: ( )( )2 323 2312 2i porefp ik s k sVCV Cs s s k kττ+ × + ×= × + × + × +                      (11) For this study an integral/proportional (Fig. 6) solution has been chosen as voltage regulator, where ki, kp are the integral and proportional coefficients respectively and τ1 is the time constant of a noise-rejection low-pass filter.             Fig. 6 IP Regulator  The close-loop transfer function of the system is:  2123 21112 2oprefi i iV skV C Cs s sk k kττ+ ×=     ×+ + +                           (12)  The equation (12) shows that the IP solution cancels a slow zero from the transfer function improving the dynamics of the regulator.   If the poles of the system (s0, s1 and s2) are placed on the Butterworth circle with the radius ωo such as: so = - ωo, 431πωjoes =  and432πωjoes−= , then the coefficients kp and ki are:  ( ) 32 1 2pCkτ=× + ×                                                   (13) ( )3 232 1 2iCkτ=× + ×                                                (14) If the load resistor is considered (RL), then the coefficients become [12]: ( )( )3132 211 2iLTkT Rττ+=+                                               (15) ( )( )211111 2pLTkR Tττ + = −  +                                      (16) where T = RL×C.  5. Simulation Results  To validate the above study, the Simetrix 5.3 software platform has been used to simulate the proposed topology but also the simple and the two-cascade boost converters. For all the above circuits, the values of the element have been very conservative chosen as: Vb =12 V, L = 100 µH, rL = 0.1 Ω, C = 10 µF, Vd = 1 V, RL = 50 Ω, rdson = 50 mΩ and the switching frequency of fs = 50 kHz. Figures 7 & 8 show the simulation model for the proposed boost converter and the output voltage. The model has been tune to give the maximum output voltage of 122.1 V for a duty cycle of 85 percentages. This gives a boost factor of 10.1 compared to 11.9 estimated according to (9).            Fig.7 Double-boost converter- simulation model    ● ● ● ● ● ● ● ● ● ● Vref PWM Ramp Generator Vo IP Reg. C RL Vb L L D1 D2 D3 Q1 Q2 iks 2refV + + 2oV  - kp 2C s× - 111 sτ+ × 50R4D4D550uL3100mR3100mR110uC1D112V150uL1S1V2 S3D1-cathode45IC 10  10  1 D2 3 3 t  176              Fig.8 Double-boost converter- maximum output voltage  In figure 9 & 10, the simple boost simulation model and maximum output voltage are shown. The maximum output voltage achieved was 52.7 V for a duty cycle of 80 percentages. The boost factor is 4.4 compared with and estimated of 4.67.        Fig.8 Simple-boost converter- simulation model               Fig.9 Simple-boost converter- maximum output voltage  The two-cascade boost converter simulation model is shown in figure 10 and the maximum output voltage in figure 11.          Fig.10 Two-cascaded boost converter- simulation model The two-cascade boost converter simulation model is shown in figure 10 and the maximum output voltage in figure 11. The maximum output voltage of 82.1 V is achieved for 80 percentages duty cycle which represents a boost factor of 6.84 compared to 7.91. It can also be observed a very instable starting period, same conclusion as in [4].                Fig.11 Simple-boost converter- maximum output voltage   Figures 12 & 13 show the comparative output voltages between the simple and two-cascade boost and between the simple and the proposed double-boost respectively, while figure 14 shows all three output voltages for a better comparison.              Fig.12 Double-boost and simple-boost comparison               Fig.13 Double-boost and two-cascade comparison    122.1 V V2 S1100uL112V1D110uC1100mR150R4 100uL2U1INV10uC2S2 50R4100mR110uC112V1100uL1S1V2100mR2D1 D2  82.1 V    52.7 V 177                Fig.14 Output voltage of all studied converters  From the above graphs, it is obvious the boost factor for the two-cascade converter is not double of the simple boost, while the proposed double-boost is more than double. Another aspect studied was to verify the assumption that the charging currents through the two inductors could be considered equal. Fig, 15 shows the two current and the current through diode 3 on normal scale, while Fig. 16 shows the zoom of the moment when these entire three current joint together.               Fig. 15 Inductors and diode 3 currents     Fig. 13         Fig. 16 Inductors and diode 3 currents-zoom   From Fig. 16 results a 0.68 percentage difference between the two inductor current, which makes very much acceptable the initial assumption.  6. Conclusion The present paper has presented a new boost topology which ensures a significant improvement on boost factor; a boost factor of 10 was proven even with very conservative parameters’ values of the components. The new double-boost converter has been modeled and the simulation results are presented in comparison with classical known boost converters.  References [1] J.A. Morales-Saldaňa, et al, Modeling of a Cascade Boost Converter with Single Switch, The 32nd Annual Conference of the IEEE Industrial Electronics Society, 2006 [2] W. Lee, et al, “Interleaved ZVT Boost Converters with Winding Inductors and Built-In LC Low-Pass Output Filter Suitable for Distributed Fuel Cell Generation System”, 38th IEEE Power Electronics Specialists Conference, 2007 [3] H.C. Iu, “Experimental Study of Instabilities in Two parallel-Connected Boost Converter under Current Mode Control”, 11th European Conference on Power Electronics and Applications. 2005 [4] M. Veerachary, “General Rules for Signal Flow Graph Modeling and Analysis of DC-DC Converters”, IEEE Trans. On Aerospace and Electronics Systems, Vol. 40, No. 1, pp. 259-271, Jan. 2004 [5] N. Vazquez, L. Estrada, C. Hernandez and E. Rodriguez, « The Tapped-Inductor Boost Converter”, IEEE International Conference on Industrial Electronics (ISIE), 2007 [6] Y. Bercovich, B. Axelrod, S. Tapuci and A. Ioinovici, “A Family of Four-Quadrant DC-DC Converters”, 38th IEEE Power Electronics Specialists Conference, 2007 [7]  G. Thiele and E. Bayer, Voltage Doubler/Tripler Current-Mode Charge Pump Topology with Simple “Gear Box”, 38th IEEE Power Electronics Specialists Conference, 2007 [8] B.S. Min, N.J. Park and D.S. Hyun, “A Novel Current Sharing Technique for Interleaved Boost Converter”, 38th IEEE Power Electronics Specialists Conference, 2007 [9] I. Batarseh, Power Electronics Circuits, John Wiley & Sons, Inc. 2004, pp. 189-199 [10] Q. Zhou, Y. Huang, F. Zeng and Q-S. Chen, “Dynamic analysis of DC-DC Converter Based on Its Nonlinear Characteristics”, The 32nd Annual Conference of the IEEE Industrial Electronics Society, 2006 [11] H. Komurcugil, “A PI-Type Self Tuning Fuzzy Controller for Dc-Dc Boost Converters”, The 30th Annual Conference of the IEEE Industrial Electronics Society, 2004 [12] D.V. Nicolae, Single-Phase Unity Power Factor Rectifier with Improved Dynamic Response for Non-linear Load, International Review of Electrical Engineering, Vol.2 No. 4, pp. 537-543, July-August 2007     IL1 IL2 ID3  178

A new dc-dc double-boost typology for enhancing the voltage ratio

Abstract In this paper anew boost topology is proposed. The circuit is similar with two parallel boost dc-to-dc converters, but the two inductors are charged in parallel and release energy in series, thus enhancing the voltage boost ratio. After a short analysis of the circuit, a comparative study with other classic boost converter (single boost and twocascade) is presented. The simulation results show a net improvement of the boost ratio for the new proposed topology

Nicolae, D V

van Rensburg, J F J

Name not available

  
 
A NEW DC-DC DOUBLE-BOOST TOPOLOGY FOR  
ENHANCING THE VOLTAGE RATIO 
 
DV Nicolae* and JFJ van Rensburg** 
*Tshwane University of Technology, Electrical Engineering Department, P. Bag X680, Pretoria, 0001, South Africa 
**Vaal University of Technology, Vanderbijlpark, South Africa 
danaurel@yebo.co.za; hannesvr@vut.ac.za   
 
 
 
ABSTRACT 
In this paper anew boost topology is proposed. The circuit 
is similar with two parallel boost dc-to-dc converters, but 
the two inductors are charged in parallel and release 
energy in series, thus enhancing the voltage boost ratio. 
After a short analysis of the circuit, a comparative study 
with other classic boost converter (single boost and two-
cascade) is presented. The simulation results show a net 
improvement of the boost ratio for the new proposed 
topology. 
 
KEY WORDS 
DC-DC conversion, boost converter, modelling, 
simulation 
 
 
 
1.  Introduction 
 
An increased boost factor suits the many emerging 
applications in the automotive industry, 
telecommunications industry, and IT industry as well as 
power generation via fuel cells, photovoltaic arrays and 
wind turbines [1-8].  The basic boost topology does not 
provide a high boost factor.  This has led to many 
proposed topologies such as the tapped-inductor boost, 
cascaded boost and interleaved boost converters [5-8].  
This paper introduces another variation which provides a 
higher boost factor and also provides for the possibility to 
gear up or down thus extending the control range. 
Although control methods such as fuzzy logic [11], 
sliding mode control [14] and others [10, 12, and 14] are 
available, a simple PI controller is used to verify the 
proposed double -boost topology. 
 
 
2.  Proposed Model 
 
Fig. 1 shows the proposed topology. The inductors L1 
& L2 have the same values, the diodes D1-D3 are the same 
type and the same assumption was for the transistors (Q1 
& Q2). Each inductor has its own switch and thus is 
similar with the paralleling of two single/classic 
converters.  
 
 
 
 
 
 
 
 
 
 
 
Fig. 1 Proposed Model 
 
 
2.1 Equivalent Diagram in ON State 
 
Let us firstly consider ideal components. When the 
transistors Q1 & Q2 are in ON state, the proposed 
topology transfers energy from the dc source (Vb) into the 
inductors L1 & L2 as can be seen in Fig.2, where i1 is the 
current through inductor/transistor 1, i2 is the current 
through inductor/transistor 2, io is the output current 
through load RL and C is the smoothing capacitor. 
 
 
 
 
 
 
 
 
 
 
Fig.2 Equivalent diagram for Q1 = Q2 = ON 
 
2.2 Equivalent Diagram in OFF State 
 
 
During the OFF state, the two inductors are connected 
in series, as shown in the equivalent diagram (Fig. 3). 
 
+ 
Vb 
L1 L2 
Q2 Q1 
D1 
D2 
D3 
C 
RL 
● 
● 
● ● 
● 
● ● ● 
● 
● 
D1 
L 
L 
+ 
Vb 
● 
● 
C 
Io 
Q1 Q2 i2 i1 
RL 
● 
● ● ● 
Vo 
● ● 
625-047 174
  
 
 
 
 
 
 
 
 
 
 
Fig.3 Equivalent diagram for Q1 = Q2 = OFF 
 
2.3 Boost Factor 
The switching frequency is high enough so the 
differential equations governing the circuit could be 
linearized. For the charging interval (Q1 = Q2 = ON), the 
voltage across each inductor is Vb and the currents i1(t) 
and i2(t) could be written as: 
( ) ( ) ( )1 2 0b L
V
i t i t t I
L
= = +  (1) 
where IL(0) is the initial current through inductor at t = 0. 
When the transistors are turned OFF at t = δT (δ being 
the duty cycle), the voltage across inductors is Vo – Vb 
and the current iL(t) is: 
( ) ( ) ( )
2
b o
L L
V V
i t t T I T
L
δ δ
−
= − +  (2) 
Evaluating eq. (1) at t = δT and (2) at t = T, the system 
becomes: 
( ) ( ) ( ) ( )1 2 0bL L
V
I T i t T i t T T I
L
δ δ δ δ= = = = = +  (3) 
( ) ( ) ( ) ( )0
2
b o
L L L
V V
I i t T T T I T
L
δ δ
−
= = = − +  (4) 
The converter is design to operate in continuous mode 
and IL(0) = IL(δT). From the system of (2) and (3) the 
boost factor Mp for the proposed circuit can be deducted: 
2
1
o
p
b
V
M
V δ
= =
−
 (5) 
As can be noticed, the boost factor of the proposed 
topology is double as regarded to the simple boost 
converter. 
 
3. Boost Comparison 
 
In order to enhance the advantage of the proposed boost 
topology, a boost factor comparison with a single and 
two-cascaded converter is necessary. This should be done 
taking in consideration the real values of components. 
 
 
3.1 Simple-boost converter 
As presented in [9], the boost factor (Ms) depends on 
inductor resistance (rL) as: 
( )
( )
1/ 1
1
L
s
L
r
M
R
δ
δ
 
= − + 
−  
 (6) 
When taking in consideration voltage drop across the 
diode (Vd) and transistor resistance in saturation (rdson), 
the boost factor becomes: 
( )
( )
1/ 1
1
swon d
s
L b
r V
M
R V
δ
δ
δ
 
= − + − 
−  
 (7) 
 
3.2 Two-cascaded boost converter 
When two identical simple converters are connected in 
cascade (Fig. 4), the boost factor (Mc) is affected by the 
capacitor (C) in the first unit and switching 
synchronization. Eq. (8) shows the boost factor for the 
cascade. 
 
 
 
 
 
 
 
 
 
Fig.4 Double cascade boost converter 
 
( )
( )
( )
2 / 1/ 1
1 1
s L swon d
c
L L b
T r r V
M
R C R V
δ δ
δ
δ δ
    + = − − + −    
− −        
 (8) 
3.3 Proposed double-boost converter 
For this topology, all the real parameters should be 
taken in consideration at once. As can be noticed, the 
currents through inductors are slightly uneven, but for a 
good approximation they still can be considered equal. 
Then the boost factor could be written as: 
 ( )
( )
2
2 / 1
1
L swon d
L b
r r V
M
R V
δ
δ
δ
 +
= − + − 
−  
 (9) 
It can be seen that the inductance resistor and voltage 
across transistor resistor in ON state are considered with 
unity factor because the charging is parallel and 
independent one of each other, while the diode voltage 
drop has a coefficient two because they both are in series 
when the energy is transferred to the output. 
 
 
 
Vo 
● 
iL 
● ● 
+ 
Vb 
VL1 
D3 
● 
D2 
VL2 
iC 
C R
Io 
● ● 
D1 D2 
L L 
C C 
Q1 Q2 
RL Vb 
+ 
175
4. Control System 
 
For this study, a simple IP controller has been used, as 
shown in Fig. 5. 
 
 
 
 
 
 
 
 
 
 
 
 
Fig.5 Double-boost converter, control system 
 
In the steady state, the power balance between input and 
output can be written as: 
( )21b s o o odV I V V I
C dt
= ⋅ +  (10) 
Based on this dynamic equation, majority of authors 
have proposed a classic PI regulator. But the closed-loop 
transfer function of this type of regulator has two zeros: 
( )( )2 3
2
3 23
1
2 2
i po
ref
p i
k s k sV
CV C
s s s k k
τ
τ
+ × + ×
=
 
× + × + × + 
 
                    (11) 
For this study an integral/proportional (Fig. 6) solution 
has been chosen as voltage regulator, where ki, kp are the 
integral and proportional coefficients respectively and τ1 
is the time constant of a noise-rejection low-pass filter. 
 
 
 
 
 
 
 
 
 
 
 
 
Fig. 6 IP Regulator 
 
The close-loop transfer function of the system is: 
 
2
1
2
3 21
1
1
2 2
o
pref
i i i
V s
kV C C
s s s
k k k
τ
τ
+ ×
=
     ×
+ + +     
     
                 (12) 
 
The equation (12) shows that the IP solution cancels a 
slow zero from the transfer function improving the 
dynamics of the regulator.  
 
If the poles of the system (s0, s1 and s2) are placed on the 
Butterworth circle with the radius ωo such as: so = - ωo, 
4
3
1
π
ω
j
oes =  and
4
3
2
π
ω
j
oes
−
= , then the coefficients kp and 
ki are:  
( ) 32 1 2p
C
k
τ
=
× + ×
                                                   (13) 
( )3 232 1 2
i
C
k
τ
=
× + ×
                                                (14) 
If the load resistor is considered (RL), then the 
coefficients become [12]: 
( )
( )
3
1
3
2 2
1
1 2
i
L
T
k
T R
τ
τ
+
=
+
                                               (15) 
( )
( )
2
1
1
1
1
1 2
p
L
T
k
R T
τ
τ
 + = −
  +
 
                                     (16) 
where T = RL×C. 
 
5. Simulation Results 
 
To validate the above study, the Simetrix 5.3 software 
platform has been used to simulate the proposed topology 
but also the simple and the two-cascade boost converters. 
For all the above circuits, the values of the element have 
been very conservative chosen as: Vb =12 V, L = 100 µH, 
rL = 0.1 Ω, C = 10 µF, Vd = 1 V, RL = 50 Ω, rdson = 50 mΩ 
and the switching frequency of fs = 50 kHz. 
Figures 7 & 8 show the simulation model for the 
proposed boost converter and the output voltage. The 
model has been tune to give the maximum output voltage 
of 122.1 V for a duty cycle of 85 percentages. This gives 
a boost factor of 10.1 compared to 11.9 estimated 
according to (9). 
 
 
 
 
 
 
 
 
 
 
 
Fig.7 Double-boost converter- simulation model 
 
 
 
● ● 
● 
● 
● ● 
● 
● ● 
● 
Vref 
PWM 
Ramp Generator 
Vo 
IP Reg. 
C RL Vb 
L L D1 D2 D3 
Q1 Q2 
i
k
s
 
2
refV
 
+ 
+ 
2
oV  
- 
kp 
2
C s×
 
- 
1
1
1 sτ+ ×
 
50
R4
D4
D5
50u
L3
100m
R3
100m
R1
10u
C1
D1
12
V1
50u
L1
S1V2 S3
D1-cathode
45
IC
 
10  
10  
1 
D2 
3 
3 t  
176
  
 
 
 
 
 
 
 
 
 
 
 
 
Fig.8 Double-boost converter- maximum output voltage 
 
In figure 9 & 10, the simple boost simulation model and 
maximum output voltage are shown. The maximum 
output voltage achieved was 52.7 V for a duty cycle of 80 
percentages. The boost factor is 4.4 compared with and 
estimated of 4.67. 
 
 
 
 
 
 
 
Fig.8 Simple-boost converter- simulation model 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Fig.9 Simple-boost converter- maximum output voltage 
 
The two-cascade boost converter simulation model is 
shown in figure 10 and the maximum output voltage in 
figure 11.  
 
 
 
 
 
 
 
 
Fig.10 Two-cascaded boost converter- simulation model 
The two-cascade boost converter simulation model is 
shown in figure 10 and the maximum output voltage in 
figure 11. The maximum output voltage of 82.1 V is 
achieved for 80 percentages duty cycle which represents a 
boost factor of 6.84 compared to 7.91. It can also be 
observed a very instable starting period, same conclusion 
as in [4]. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Fig.11 Simple-boost converter- maximum output voltage 
 
 
Figures 12 & 13 show the comparative output voltages 
between the simple and two-cascade boost and between 
the simple and the proposed double-boost respectively, 
while figure 14 shows all three output voltages for a better 
comparison. 
 
 
 
 
 
 
 
 
 
 
 
 
 
Fig.12 Double-boost and simple-boost comparison 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Fig.13 Double-boost and two-cascade comparison 
 
 
 
122.1 V 
V2 S1
100u
L1
12
V1
D1
10u
C1
100m
R1
50
R4
 
100u
L2
U1
INV
10u
C2
S2 50
R4
100m
R1
10u
C1
12
V1
100u
L1
S1V2
100m
R2
D1 D2
 
 
82.1 V 
 
 
 
52.7 V 
177
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Fig.14 Output voltage of all studied converters 
 
From the above graphs, it is obvious the boost factor for 
the two-cascade converter is not double of the simple 
boost, while the proposed double-boost is more than 
double. 
Another aspect studied was to verify the assumption that 
the charging currents through the two inductors could be 
considered equal. Fig, 15 shows the two current and the 
current through diode 3 on normal scale, while Fig. 16 
shows the zoom of the moment when these entire three 
current joint together. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Fig. 15 Inductors and diode 3 currents 
 
 
 
 
Fig. 13 
 
 
 
 
 
 
 
 
Fig. 16 Inductors and diode 3 currents-zoom 
 
 
From Fig. 16 results a 0.68 percentage difference 
between the two inductor current, which makes very 
much acceptable the initial assumption. 
 
6. Conclusion 
The present paper has presented a new boost topology 
which ensures a significant improvement on boost factor; 
a boost factor of 10 was proven even with very 
conservative parameters’ values of the components. The 
new double-boost converter has been modeled and the 
simulation results are presented in comparison with 
classical known boost converters. 
 
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A new dc-dc double-boost typology for enhancing the voltage ratio

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