Register connection: A new approach to adding registers into instruction set architectures

Abstract

Code optimization and scheduling for superscalar and superpipelined processors often increase the register requirement of programs. For existing instruction sets with a small to moderate number of registers, this increased register requirement can be a factor that limits the e ectiveness of the compiler. In this paper, we introduce a new architectural method for adding a set of extended registers into an architecture. Using a novel concept of connection, this method allows the data stored in the extended registers to be accessed by instructions that apparently reference core registers. Furthermore, we address the technical issues involved in applying the new method toanarchitecture: instruction set extension, procedure call convention, context switching considerations, upward compatibility, e cient implementation, compiler support, and performance. Experimental results based onaprototype compiler and execution driven simulation show that the proposed method can signi cantly improve the performance of superscalar processors with a small or moderate number of registers.