2009 IEEE International Conference on Industrial Technology - (ICIT) : Churchill, Victoria, Australia, 2009.02.10-2009.02.1

Dousoky Gamal M.

Ninomiya Tamotsu

Shoyama Masahito

Nagasaki University's Academic Output SITE: NAOSITE

FPGA-Based Design and Implementation of Spread-Spectrum Schemes for Conducted-Noise Reduction in DC-DC ConvertersGamal M. Dousoky1) Masahito Shoyama1) Tamotsu Ninomiya2)1) Kyushu University, 744 2-626-1 motooka, nishi-ku, Fukuoka, 819-0395 Japan2) Nagasaki University, 1-14 Bunkyo-machi, Nagasaki, 852-8521 JapanE-mail: dousoky@ieee.orgAbstract- In this paper many spread-spectrum schemes, several of which are new, have been designed and implemented for conducted-noise reduction in DC-DC converters. A field-programmable gate array (FPGA) has made substantial improvements in price and performance throughout the past few years. The implementation of the schemes has been accomplished by using FPGA-based controller.A breadboard circuit has been built-up for investigating the effect of all the proposed schemes on conducted-noise spectrum in DC-DC converters. Furthermore, a comparative study has been carried-out to reach the most efficient scheme in spreading the conducted-noise spectrum.Experimental results show that randomizing each of carrier frequency, duty-ratio, and the pulse position parameters significantly improves the conducted-noise spectrum and effectively reduces the noise peaks at both high and low frequency ranges. I. INTRODUCTIONDC-DC converters are important in portable electronic devices such as cellular phones , laptop computers, and electric vehicles, which are supplied with power from a DC power source such as batteries, photovoltaic cells, or fuel cells. Such electronic devices often contain several sub-circuits, with each sub-circuit requiring a unique voltage level different from that supplied by the source, [1] - [3]. Switching power converters have been reported to generate common-mode and differential-mode conducted-noise in addition to radiated-noise. They may cause serious problems by generating such switching noise. Although switching converters produce significant amounts of switching noise, they are also required to operate inside electromagnetic interference (EMI) sensitive applications, [4] and [5]. This research aims to reduce the switching noise produced by DC-DC converters.Traditional tools for EMI suppression are related to the use of filters and shielding techniques. But these tools are bulky and require expensive passive components, which makes them unsuitable for space-limited and price-sensitive portable devices, [5] and [6]. Alternative, pre-emptive EMI mitigation techniques eliminate the need for EMI filters by spreading the switching converters noise over a frequency range, [7]–[14]. By using these techniques, the noise generated by the Switching-Mode Power Supplies (SMPS) can be spread across a well defined frequency band. As a result, the average spectral power density of the broadband noise can thus be drastically reduced, [15].FPGA is an attractive hardware design option. It has made substantial improvements in price and performance throughout the past few years, [16]. For an excellent overview of the classical and recent developments in FPGA technology, focusing on industrial control system applications, the reader is referred to [17]. Although FPGA implementation is now widespread in a range of military, defense, and signal processing applications, it is much flexible than analog control, becoming lower cost, and applicable for power supply applications. The implementation of the spread-spectrum schemes has been accomplished by using FPGA-based digital controller.The paper is organized as follows: Section II presents spread-spectrum schemes in DC-DC converters.  The design and implementation of the proposed FPGA-based controller which includes pseudorandom streams generator and digital pulse-width modulator are addressed in section III. Section IV describes the details of the experimental test circuit. Experimental results and discussion are presented in section V. Finally, conclusions and future work have been presented in section VI.II. SPREAD-SPECTRUM SCHEMESIN DC-DC CONVERTERSAccording to Fig. 1, Tk is the duration of the kth cycle, k is the duration of the on-state within this cycle, and k is thedelay from the starting of the switching cycle to the turn-on within the cycle. Note that the duty ratio is dk= k/ Tk and theswitching frequency Fk=1/Tk.978-1-4244-3507-4/09/$25.00 ©2009 IEEE Page 527Fig. 1. Randomization parameters in the switching signal.The switching function q(t) consists of a series of such switching cycles. In order to spread the frequency spectrum of the switching noise, {Fk, dk, or k} can be randomized. Table I summarizes all the possible schemes that can be carried-out for this purpose.Some randomization schemes used in power electronics are, [7] - [14]:Randomized pulse position modulation (RPPM):k changes; Fk, and dk are fixed;Randomized pulse width modulation (RPWM):dk changes; Fk, and k are fixed; Randomized carrier frequency modulation with fixed duty ratio (RCFMFD): Fk, changes; dk, and k are fixed;Randomized carrier frequency modulation with variable duty ratio (RCFMVD): Fk, and dk change; k is fixed.On the other hand, as in Table I, still another three different randomization schemes which haven’t been addressed before; due to hardware limitations and the complexity of the control circuit. These schemes are:Randomized duty ratio, randomized pulse position modulation with fixed carrier frequency(RDRPPMFCF): dk, and k change; Fk is fixed;Randomized carrier frequency, randomized pulse position modulation with fixed duty ratio(RCFRPPMFD): Fk, and k change; dk is fixed;Randomized carrier frequency, randomized duty ratio, with randomized pulse position modulation (RRRM): Fk, dk, and k change.TABLE ITHE RANDOMIZATION PARAMETERS FOR THE SCHEMES.Randomization ParametersCase SchemeFk dk kk Remarks(a) PWM Const. Const. Const. Const. Basic(b) RPPM Const. Const. Rand. Const. Ad.*(c) RPWM Const. Rand. Const. Rand. Ad.*(d) RDRPPMFCF Const. Rand. Rand. Rand. New(e) RCFMFD Rand. Const. Const. Rand.; Synch. Ad.*(f) RCFRPPMFD Rand. Const. Rand. Rand.; Synch. New(g) RCFMVD Rand. Rand. Const. Rand. Ad.*(h) RRRM Rand. Rand. Rand. Rand. NewAd.*: Addressed before in power electronics publications.Now, with the flexibility and programmability of the FPGA technology, the above new schemes have been designed, implemented and addressed in this paper. Moreover, the other schemes, used before in power electronics, have been designed and implemented as well. Furthermore, all schemes have been experimentally investigated and conducted-noise spectrums have been compared in the following sections.III. DESIGN AND IMPLEMENTATION OF THEPROPOSED FPGA-BASED CONTROLLERThis section presents the design and implementation of theproposed FPGA-based controller which includes pseudo-random stream generator and digital pulse-width modulator.A. Pseudorandom Streams GeneratorAs discussed in the previous section, in order to spread the noise spectrum, {Fk, dk, or k} can be randomized. Hence three random number generators are needed to realize all the addressed schemes.Fig. 2. The proposed pseudorandom streams generator.m-LFSR150110100011111100PseudorandomBitm-LFSR16-bitPseudorandom Streamm-LFSR11m-LFSR0112-bitPseudorandom Stream10-bitPseudorandom Stream1Tkkk10q(t)tPage 528clkreset0reset1TNWNENVgs1Vgs2A pseudorandom streams generator has been constructedfor this purpose. As shown in Fig. 2, the proposed construction uses several maximum length linear feedback shift registers (m-LFSRs) in parallel. The use of m-LFSRs is due to the fact that the sequence generated by the m-LFSRs has a maximum period. For different m-LFSRs output bits, different initial contents of m-LFSRs (seeds) have been used. The taps are XOR'd sequentially with the output and then fed back into the leftmost bit.The designed pseudorandom streams generator deliversthree different random streams; (16-bit, 12-bit, and 10-bitstreams). The 16-bit stream is composed of the output bits of the m-LFSRs. Furthermore, the 12-bit and 10-bit streams are composed of some of these bits with different arrangements. The m-LFSRs are clocked regularly; i.e., the movement of the data in all the m-LFSRs is controlled by the same clock.Only at the beginning of every switching cycle, the random output bits are converted into an integer numbers (RFS, RDS,and RES) and used in the digital pulse-width modulator (DPWM). However, the other generated random output bits are discarded.B. Digital Pulse-Width ModulatorAt the beginning of every switching cycle, the DPWM achieves the following assignments:1. Converting the pseudorandom (16-bit, 10-bit and 12-bit) streams into integer numbers (RFS, RDS and RES)with ranges from zero to (65535, 1023 and 4095), respectively.2. Calculating randomization parameters for the started switching cycle and the needed number of steps to fulfill them as in the following equations:fsw = fL + K * RFS (1)TN = fclk / fsw (2)WN = TN * (dL + RDS)/1E4 (3)     EN = TN * (eL + RES)/ 1E4     (4)Where;fsw : Switching frequencyfL : Lower frequency limit, (taken 234.5 kHz)*K: Constant (taken K=2*) for achieving the required  randomized frequency range (234.5~365.5 kHz)*RFS, RDS,and RES: Pseudorandom output streams converted into  integer numbersTN : Needed number of steps to fulfill the switching frequencyfclk : Clock frequencyWN : Needed number of steps to fulfill the duty-ratiodL : Lower duty-ratio limit, (taken 2488)*EN : Needed number of steps to fulfill the pulse positioneL : Lower pulse position limit, (taken 1500)*1E4: For normalizing both of (dL+RDS) and (eL+RES) to be a   fraction of one, (since their maximum values have been   considered as 1E4).*: For case RRRM, (Fk=234.5~365.5 kHz, dk=0.249~0.351 and k=0.15~0.56 of Tk).3. Generating the digital pulse-width modulatedwaveforms (Vgs1,2) with the commanded randomization parameters. As shown in Fig. 3, the designed DPWM uses a clocked-counter that increments (up to TN) and resets at the end of every switching cycle of the PWM (see reset1 signal). When the counter value lies between the reference values {EN, EN+WN}, the controller keeps the PWM output state high, else low. In this way, the digital pulse-width modulated waveforms (Vgs1,2) are generated with the commanded randomization parameters.Fig. 3. VHDL simulation of the proposed FPGA-based controller with RRRM scheme.IV. EXPERIMENTAL VERIFICATIONAll the spread-spectrum schemes, described previously, have been designed and implemented using an Altera FPGA. A synchronous buck converter topology has been selected in order to improve efficiency and reduce heat loss. The output inductor and capacitor have been sized such that the converter operates in continuous conduction mode (CCM). Table IIillustrates the converter power-circuit parameters.TABLE IITHE CONVERTER POWER-CIRCUIT PARAMETERS.Symbol Description ValueVin Input voltage (V) 12Vo Output voltage (V) 3.3Io Output current (A) 5fcsw Center switching frequency (kHz) 300L 4.3C 470Cin 100Page 52912 VFGQ1Q24.3uHL100uFCin470uFC1uFCc3.3mH3.3mH0.66RLVin12VLISN50uHx21uFx2 0.1uFx250 ohm x20.22uF 0.22uF 2200pFx2 2200pFx2Fig. 4. Experimental circuit for conducted-noise measurements.The conducted-noise has been measured across the input terminals of the converter using line impedance stabilization networks (LISN), [5]. Fig. 4 describes Experimental circuit for conducted-noise measurements. The LISN is used to standardize the input impedance seen from the converter input and sense the conducted-noise, which is measured by an EMI receiver. Noise measurements have been taken at:Vin = 12 V, Vo = 3.3 V, and Io = 5 A.V. RESULTS AND DISCUSSIONFig. 5 illustrates the measured conducted-noise spectrum of the converter with different spread-spectrum schemes. It is clear that the noise peaks are concentrated in two regions; the first region at the low frequency range (0.15 ~ 1 MHz) around the center switching frequency, and the other region at the high frequency range (1 ~ 30 MHz).Comparing Fig. 5.(b ~ d) with Fig. 5.(e ~ h) reveals that the switching frequency, as a randomization parameter, is more efficient in spreading the conducted-noise than the duty-ratio or the pulse position parameters.Fig. 6 presents the effect of the spread-spectrum schemes on the conducted-noise peak reduction at both low and high frequency ranges. This comparison has been carried-out by subtracting the conducted-noise peak of the PWM scheme from that of the spread-spectrum scheme, at both of the two regions. It can be seen that the RCFRPPMFD and RCFMVD schemes achieve a similar performance.The RPWM scheme gives the worst performance. It poorly improves the conducted-noise spectrum at the high frequency range. Moreover, it increases the conducted-noise peak at the low frequency range. However, the RRRM scheme attains the best performance. It provides the highest conducted-noise peak reduction at the low frequency range. Furthermore, it decreases the conducted-noise peak at the high frequency range by 7.8dB.VI. CONCLUSIONSMany spread-spectrum schemes, several of which are new, have been designed and implemented using FPGA for conducted-noise reduction in DC-DC converters. Moreover, the effect of using such schemes on the conducted-noise characteristics of the converter has been experimentally investigated. It can be concluded that:1. The RPWM scheme gives the worst performance. It poorly improves the conducted-noise spectrum at the high frequency range. Moreover, it increases the conducted-noise peak at the low frequency range.2. The switching frequency, as a randomization parameter, is more efficient in spreading the conducted-noise than the duty-ratio or the pulse position parameters.3. The RRRM scheme attains the best performance. It provides the highest conducted-noise peak reduction at the low frequency range. Furthermore, it decreases the conducted-noise peak at the high frequency range by 7.8dB.Currently, a detailed study of the RRRM scheme is being carried-out by the authors. It includes calculation/estimation of the noise spectrum, and sweeping the three randomization parameters for reaching the values which achieve the best conducted-noise spectrum spreading.Page 530102030405060700.1 1 10 100Frequency (MHz)ConductedNoise(dBuV)QP(B)PWM(a) PWM, (Fk=300 kHz, dk k=0.0).102030405060700.1 1 10 100Frequency (MHz)ConductedNoise(dBuV)QP(B)PWMRPPM(b) RPPM, (Fk=300 kHz, dk k=0.15~0.56 of Tk).102030405060700.1 1 10 100Frequency (MHz)ConductedNoise(dBuV)QP(B)PWMRPWM(c) RPWM, (Fk=300 kHz, dk k=0.0).102030405060700.1 1 10 100Frequency (MHz)ConductedNoise(dBuV)QP(B)PWMRDRPPMFCF(d) RDRPPMFCF, (Fk=300 kHz, dk=0.249~0.351, k=0.15~0.56 of Tk).102030405060700.1 1 10 100Frequency (MHz)ConductedNoise(dBuV)QP(B)PWMRCFMFD(e) RCFMFD, (Fk=234.5~365.5 kHz, dk=0.3, k=0.0).102030405060700.1 1 10 100Frequency (MHz)ConductedNoise(dBuV)QP(B)PWMRCFRPPMFD(f) RCFRPPMFD, (Fk=234.5~365.5 kHz, dk=0.3, k=0.15~0.56 of Tk).102030405060700.1 1 10 100Frequency (MHz)ConductedNoise(dBuV)QP(B)PWMRCFMVD(g) RCFMVD, (Fk=234.5~365.5 kHz, dk k=0.0).102030405060700.1 1 10 100Frequency (M Hz)ConductedNoise(dBuV)QP(B)PWMRRRM(h) RRRM, (Fk=234.5~365.5 kHz, dk=0.249~0.351, k=0.15~0.56 of Tk).Fig. 5. The measured conducted-noise spectrum of the converter with different spread-spectrum schemes.CISPR 22 Class B LimitsCISPR 22 Class B LimitsCISPR 22 Class B LimitsCISPR 22 Class B LimitsCISPR 22 Class B LimitsCISPR 22 Class B LimitsCISPR 22 Class B LimitsCISPR 22 Class B LimitsPage 5312.27.65.217.4282.67.81.68.847.8-0.4-11357911Low Frequency Range (0.15MHz - 1 MHz) High Frequency Range (1MHz - 30 MHz)Conducted-NoisePeakReduction(dB)RPPMRPWMRDRPPMFCFRCFMFDRCFRPPMFDRCFMVDRRRMFig. 6. The effect of the spread-spectrum schemes on the conducted-noise peak reduction.REFERENCES[1] L. Palma, M. H. Todorovic, and P. Enjeti, “Design Considerations for a Fuel Cell Powered DC-DC Converter for Portable Applications”, Applied Power Electronics Conference and Exposition (APEC '06), pp. 1263-1268, Mar 2006.[2] A. P. Dancy and A. P. Chandrakasan, “Ultra Low Power Control Circuits for PWM Converters”, IEEE Power Electronics Specialists Conference (PESC’97), pp. 21-27, 1997.[3] A. Boni, A. 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FPGA-based design and implementation of spread-spectrum schemes for conducted-noise reduction in DC-DC converters

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Dousoky, Gamal M.

Shoyama, Masahito

Ninomiya, Tamotsu

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FPGA-based design and implementation of spread-spectrum schemes for conducted-noise reduction in DC-DC converters

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