Bohn, Christian

Koos, Christian

Vangerow, Christian v.

Zwick, Thomas

Zwickel, Heiner

English

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50GBit/s PAM-4 Driver Circuit Based on Variable Gain Distributed Power Combiner

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50 GBit/s PAM-4 Driver Circuit Based on Variable GainDistributed Power CombinerChristian v. Vangerow#, Christian Bohn#, Heiner Zwickel∗, Christian Koos∗ and Thomas Zwick##Institute of Radio Frequency Engineering and Electronics, KIT, Karlsruhe, Germany∗Institute of Photonics and Quantum Electronics, KIT, Karlsruhe, GermanyAbstract— In this work an analog driver circuit for pulseamplitude modulated data signals with four amplitude levels(PAM-4) is investigated. The driver circuit is based ona distributed combining cell, which performs the PAM-4 generation from binary input data streams. Due to thedistributed topology, the driver core provides a high analogbandwidth and is well suited for high-speed operation. Sincethe amplification of both combiner paths can be adjustedindividually, the combiner circuit offers predistortion capa-bilities when driving loads with a nonlinear transfer function.A one-stage prototype circuit using heterojunction bipolartransistors (HBTs) is implemented in a 130 nm SiGe BiCMOStechnology. Time-domain measurements prove PAM-4 signalgeneration at an output bitrate of 50 GBit/s, while the driverconsumes a DC power of 63 mW. Additionally, predistortionof the circuit is demonstrated at 25 GBit/s, leading to avariable vertical spacing of the amplitude levels.Index Terms— Distributed combiner, PAM-4, SiGe.I. INTRODUCTIONTo increase the spectral efficiency of communicationsystems, the transmission of PAM signals instead of binarysignals is of great interest. To convert multiple binarydata streams into a PAM signal typically digital-to-analogconverters (DAC) are used. At high data rates the im-plementation of conventional DAC topologies becomeschallenging due to tight timing requirements [1] and lim-ited bandwidth, especially in topologies using a lumpedoutput stage [2]. In [3] a time-interleaving DAC usingdistributed clock and output lines to overcome bandwidthlimitations is presented, demonstrating a 50 GBaud PAM-4signal. A completely distributed DAC approach featuringhigh bandwidth and high output power is presented in [2].Another technique to overcome bandwidth limitations isfrequency band interleaving, realized with multiple DACsconnected to mixer circuits and a passive multiplexerwhich combines the individual frequency spectra to avery broadband signal [4]. In addition to multi-purposeDACs, in CMOS technologies also the implementationof synchronous PAM-4 transmitters including equalizationcircuitry is popular to overcome bandwidth limitations (e.g.[5]). Since the benefits of synchronous circuits like theretiming capabilities are not necessary in all applications,the use of low-complexity PAM drivers operating withouta clock signal becomes quite attractive, thus eliminatingthe power consumption of the clock circuitry. A simpleway to create a PAM-4 signal from binary input signals isa passive power combiner with one input signal attenuatedby 6 dB [6]. To overcome disadvantages of this passivesolution like combiner losses and low isolation, transistorbased PAM driver circuits have been proposed, especiallyin the area of vertical-cavity surface-emitting lasers [7][8]. Similar to current summing DAC circuits, these PAMdrivers are typically based on lumped amplifying and com-bining stages, leading to limited suitability for applicationswhich demand both high bandwidth and high output power.To overcome this limitation a distributed power combiningtopology has been proposed to create PAM-4 signals, and aprototype circuit implemented with surface-mount deviceson a printed circuit board has been shown in [9].In this work the realization of a distributed powercombiner on chip level is presented, clearly demonstratingthe potential of this approach for high-speed operation.II. CIRCUIT DESIGNThe schematic of the investigated PAM-4 driver circuitis depicted in Fig. 1. The prototype circuit is essentiallya one-stage distributed power combiner with common-emitter amplifying stages. Similar to the well knowncircuit topology of the distributed amplifier with only oneinput, high-ohmic transmission lines are loaded with thecapacitive input and output impedances of the gain cells.Since for PAM-4 generation ideally a 6 dB gain differ-ence has to be established between the two combiner paths,this has to be reflected by different gain magnitudes of thetwo amplifying cells. To adjust the gain difference of thetwo combiner paths, the base bias voltages VB1 and VB2can be changed, which are provided by off-chip bias tees.If the base voltage is reduced, also the collector currentis reduced, which leads to a decrease of the transistor’stransconductance and therefore the gain of the amplifyingcell.The circuit is implemented in IHP’s SG13S SiGe BiC-MOS technology, which provides HBTs having a transitfrequency of 240 GHz and a seven layer metal stack. Theinput and output lines are implemented as microstrip lineswith the signal conductor located in the uppermost thickmetal layer, and the ground plane located in the lowermostPort 2ZL,in, lin/2IC2 ZL,in, lin/2ZL,out, lout/2 ZL,out, lout/2ZL,in, lin/2 ZL,in, lin/2IC1 RTerm RTerm RTerm Q1Q2VB2 off-chipPort 1VB1 off-chipPort 3Vcc off-chipFig. 1. Schematic of the one-stage distributed combiner.Emitter areas of Q1, Q2 are AE = 6× 0.12× 0.48µm2.At ≈ 6 dB gain difference the simulated DC bias valuesare VB1 = 962 mV, VB2 = 886 mV, Vcc = 1 V, IC1 = 8.0 mA,IC2 = 2.0 mA. |ZL,in|= 95Ω, |ZL,out|= 89Ω, lin = 533µm,lout = 587µm, RTerm = 50Ω.725 µm445 µmFig. 2. Photograph of the fabricated circuit. The given dimen-sions refer to the outer boundaries of the probing pads.metal layer. In this way high-ohmic transmission linescan be created with high isolation to the lossy siliconsubstrate. While the input lines exhibit the minimumpossible width of 2µm, the width of the output line isincreased to 3µm to account for the higher DC current.The characteristic impedances of the input and outputmicrostrip lines extracted from EM simulations at 50 GHzare |ZL,in| = 95 Ω and |ZL,out| = 89 Ω. Both input andoutput lines are terminated with 50 Ω resistors to ensure aflat gain response of the driver down to DC.III. MEASUREMENT RESULTSA photograph of the fabricated circuit can be seen inFig. 2. The chip contains probing pads for a ground-signal-ground (GSG) probe at the output and a GSGSG probe atthe input.The measured scattering parameters with varying VB2and constant VB1 are shown in Figs. 3 and 4. In the0 10 20 30 40 50 60−4−202468VB2 ↓VB2 ↓Frequency (GHz)Forwardgain(dB)|S31||S32|Fig. 3. Measured forward gain of the combiner circuit withvarying VB2 and constant VB1.0 10 20 30 40 50 60−40−30−20−100VB2 ↓VB2 ↓Frequency (GHz)Reflectioncoefficient(dB) |S11||S22||S33|Fig. 4. Measured reflection coefficients of the combiner circuitwith varying VB2 and constant VB1.bias state with about 6 dB gain difference the bandwidth is36 GHz in the high gain path and 48 GHz in the low gainpath. From the measured group delay depicted in Fig. 5one can observe a delay difference smaller than 1.4 psfrom 0.5 to 64 GHz in the bias state with about 6 dB gaindifference. The group delay data have been averaged usingfive frequency points for frequencies larger than 2 GHz toreduce the impact of the noisy phase measurement data.Time-domain measurements were performed using aMP1758A pulse pattern generator delivering pseudo-random binary sequence data signals with order 31 (PRBS-31), and the circuit’s output signal was captured by a DCA-J 86100C sampling oscilloscope. In Fig. 6 the driver’sPAM-4 output eye diagram at a baudrate of 25 GBaud isshown, corresponding to a bitrate of 50 GBit/s. Besides theamplitude levels with nearly equidistant spacing shown inFig. 6, the analog predistortion capability of the combineris shown in Fig. 7 at a bitrate of 25 GBit/s, where the gaindifference between the two combiner paths is changed. Byapplying predistortion, nonlinear transfer functions of thefollowing component in a communication system, e.g. aMach-Zehnder modulator, can be equalized. In the biasstate corresponding to the 50 GBit/s measurement, the0 10 20 30 40 50 604681012Frequency (GHz)Groupdelay(ps)τ31τ32Fig. 5. Measured group delay of the combiner circuit at ≈ 6 dBgain difference between the paths.Fig. 6. Output eye diagram of the driver circuit when driven withtwo 25 GBit/s PRBS-31 input signals. Horizontal scale: 5 ps/div,vertical scale: 30 mV/div.(a) (b)Fig. 7. 25 GBit/s output eye diagrams of the driver circuitwith (a) increased and (b) decreased gain difference of thetwo combiner paths. Horizontal scale: 15 ps/div, vertical scale:50 mV/div.circuit has a DC power consumption of 63 mW. Sinceabout 80% of the DC power are dissipated from the linetermination resistors, there is a great potential to reducethe power consumption with terminations consisting of aseries resistor and a large bypass capacitor. Thus, also thebiasing of the circuit could be realized via the ends of thelines without the need for bias-tees.IV. CONCLUSIONIn this work the implementation of a PAM-4 drivercircuit based on a distributed combining cell in a SiGeBiCMOS technology has been succesfully demonstrated.Despite the simplified topology using only one stage anda common-emitter amplifying cell, the circuit shows highanalog bandwidth and the PAM-4 signal generation isverified by time-domain measurements. The investigateddistributed combining cell is therefore a candidate withhigh potential for ultra-high bandwidth applications.REFERENCES[1] T. Ellermeyer, R. Schmid, A. Bielik, J. Rupeter, and M. Möller,“DA and AD converters in SiGe technology: speed and resolutionfor ultra high data rate applications,” in 36th European Conferenceand Exhibition on Optical Communication, Sept 2010, pp. 1–6.[2] A. Balteanu, P. Schvan, and S. P. Voinigescu, “A 6-bit segmentedDAC architecture with up to 56-GHz sampling clock and 6-Vppdifferential swing,” IEEE Trans. Microwave Theory Tech., vol. 64,no. 3, pp. 881–891, March 2016.[3] H. Huang, J. Heilmeyer, M. Grözing, M. Berroth, J. Leibrich, andW. Rosenkranz, “An 8-bit 100-GS/s distributed DAC in 28-nmCMOS for optical communications,” IEEE Trans. Microwave TheoryTech., vol. 63, no. 4, pp. 1211–1218, April 2015.[4] X. Chen, S. Chandrasekhar, S. Randel, G. Raybon, A. Adamiecki,P. Pupalaikis, and P. J. Winzer, “All-electronic 100-GHz band-width digital-to-analog converter generating PAM signals up to190 GBaud,” J. Lightwave Technol., vol. 35, no. 3, pp. 411–417, Feb2017.[5] T. O. Dickson, H. A. Ainspan, and M. Meghelli, “A 1.8 pJ/b 56 Gb/sPAM-4 transmitter with fractionally spaced FFE in 14 nm CMOS,”in 2017 IEEE International Solid-State Circuits Conference (ISSCC),Feb 2017, pp. 118–119.[6] S. Wolf, M. Lauermann, P. Schindler, G. Ronniger, K. Geistert,R. Palmer, S. Köber, W. Bogaerts, J. Leuthold, W. Freude, andC. Koos, “DAC-less amplifier-less generation and transmission ofQAM signals using sub-volt silicon-organic hybrid modulators,” J.Lightwave Technol., vol. 33, no. 7, pp. 1425–1432, April 2015.[7] G. Belfiore, L. Szilagyi, R. Henker, U. Jörges, and F. Ellinger,“Design of a 56 Gbit/s 4-level pulse-amplitude-modulation inductor-less vertical-cavity surface-emitting laser driver integrated circuit in130 nm BiCMOS technology,” IET Circuits, Devices Systems, vol. 9,no. 3, pp. 213–220, 2015.[8] J. Chen, Z. S. He, T. Lengyel, K. Szczerba, P. Westbergh, J. S.Gustavsson, H. Zirath, and A. Larsson, “An energy efficient 56 GbpsPAM-4 VCSEL transmitter enabled by a 100 Gbps driver in 0.25µmInP DHBT technology,” J. Lightwave Technol., vol. 34, no. 21, pp.4954–4964, Nov 2016.[9] C. v. Vangerow, D. Müller, and T. Zwick, “6 GBit/s PAM-4 signalgeneration with variable gain distributed power combiner,” in 2017IEEE Asia Pacific Microwave Conference (APMC), Nov 2017, pp.926–929.      Repository KITopen  Dies ist ein Postprint/begutachtetes Manuskript.  Empfohlene Zitierung:  Vangerow, C. v.; Bohn, C.; Zwickel, H.; Koos, C.; Zwick, T. 50GBit/s PAM-4 Driver Circuit Based on Variable Gain Distributed Power Combiner. 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Institute of Electrical and Electronics Engineers (IEEE), 2019. doi: 10.5445/IR/1000105510    Zitierung der Originalveröffentlichung:  Vangerow, C. v.; Bohn, C.; Zwickel, H.; Koos, C.; Zwick, T. 50GBit/s PAM-4 Driver Circuit Based on Variable Gain Distributed Power Combiner. 2019. IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 1–3, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/sirf.2019.8709086                Lizenzinformationen: KITopen-Lizenz 

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50GBit/s PAM-4 Driver Circuit Based on Variable Gain Distributed Power Combiner

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