Design, implementation and testing of the controller for the terabit packet switch

Abstract

The sequential greedy scheduling (SGS) is a scalable algorithm that provides non-blocking in high-capacity packet switches. We implemented the SGS scheduler in the FPGA device, and examined its scalability and speed. Then, we developed the software for design testing. Our testing software confirms the correct functioning of the scheduler. Both, the scheduler implementation, and the testing software are presented in this paper