Simulation, fabrication and assembly techniques for passive alignment of silicon photonic integrated circuits

Abstract

This thesis demonstrates a number of simulation, fabrication and assembly techniques that have been designed, developed and tested in order to facilitate the passive alignment of silicon photonic integrated circuits to allow a packaging method that can decrease the cost and time penalties associated with active alignment methods. The requirement for an affordable packaging method is highlighted and key achievements are identified in the literature.Novel and unique surface grating couplers are demonstrated to be compatible with an in-plane passively aligned packaging method which exhibit insertion losses of 1.5 dB in simulation and 2.59dB in physical characterisation with 1- and 3-dB bandwidths of 35nm and 59nm respectively, as well as having improved misalignment tolerance. Additionally, a novel means of deep-silicon etching is developed which allows customised, packaging-specific structures to be fabricated allowing passively aligned assembly within the packaging method described in this thesis by improving vision and access of a fibre, whilst decreasing the free-space propagation distance. This process has been optimised through dynamic etch parameters.Finally, this thesis also outlines a number of key innovations that allow the passive assembly of a hybrid, two-chip packaging method by using silica microspheres and epoxy, to bond and align a silicon chip to an optical fibre