While most approaches in formal methods address system correctness, ensuring
robustness has remained a challenge. In this paper we present and study the
logic rLTL which provides a means to formally reason about both correctness and
robustness in system design. Furthermore, we identify a large fragment of rLTL
for which the verification problem can be efficiently solved, i.e.,
verification can be done by using an automaton, recognizing the behaviors
described by the rLTL formula Ο, of size at most O(3β£Οβ£), where β£Οβ£ is the length of Ο. This
result improves upon the previously known bound of
O(5β£Οβ£) for rLTL verification and is closer to
the LTL bound of O(2β£Οβ£). The usefulness of
this fragment is demonstrated by a number of case studies showing its practical
significance in terms of expressiveness, the ability to describe robustness,
and the fine-grained information that rLTL brings to the process of system
verification. Moreover, these advantages come at a low computational overhead
with respect to LTL verification.Comment: arXiv admin note: text overlap with arXiv:1510.08970. v2 notes: Proof
on the complexity of translating rLTL formulae to LTL formulae via the
rewriting approach. New case study on the scalability of rLTL formulae in the
proposed fragment. Accepted to appear in ACM Transactions on Computational
Logi