This paper proposes a new architecture for EIA-709.1protocol implementation. The protocol is conventionallyimplemented with the proprietary processor and language,Neuron chip and Neuron C, respectively, where the Neuron chipconsists of 3 processors inside. The proposed architecture usesonly one general purpose processor and general ANSI C toimplement the layers of EIA-709.1 except the physical layer. Thedata link, network, and other layers are implemented onto oneRISC processor, ARM. Specifically, the data link layer of theEIA-709.1 based on predictive p-persistent CSMA/CA isimplemented. The interface between the transceiver based onpower line communication and the data link layer based on theARM is described. As a conclusion, this research shows theimprovement of performance and the compatibility with theexisting Neuron chip
