The growth of the Internet of Things (IoT) technology is transforming various industry sectors. Millions of smart devices, sensors, and actuators collaborate to monitor and manage the physical environment and human systems in the IoT paradigm. The traditional IoT is designed as a distributed system, with low-power edge devices collecting data and transmitting it to the centralized high-performance head nodes. The head nodes analyze the data, help with data visualization, and generate actionable information. However, significant challenges and overheads like bandwidth bottleneck and latency increase arise from the continuous data transmission between the edge and head devices. Edge computing is an emerging solution to the problems associated with traditional IoT. In edge computing, the computation is moved closer to the edge devices by equipping them with sufficient computation capabilities. Edge computing spans a wide variety of applications, application domains, and devices. In this dissertation, we focus on developing efficient system architectures for the edge devices.
The first step in optimizing the system architectures is to understand the requirements of the target applications. We need to characterize the applications on a system to understand the computational requirements and derive insights about the system provisioning and identify potential optimization opportunities. It is essential to characterize a variety of applications and benchmark suites since each application has different computational demands, can stress different system components, and help us better understand the system requirements. In this dissertation, we choose one of the high-impact IoT application domain suitable for edge computing, the Internet of Medical Things (IoMT), as a use-case. We propose a benchmark suite consisting of representative IoMT applications and analyze them for different execution characteristics to derive insights into their compute and memory requirements. We also present workload characterization studies of two well-known and diverse benchmark suites: SPEC CPU2017, which aims to assess the systems' high-performance computing capabilities, and GAP, which comprises of memory-bound graph applications that are critical components of data analytics workflows.
Edge computing devices will typically have strict area and power budgets, and hence, employ low-energy microprocessors with fewer computing resources. Moreover, the current generation of microprocessors has hit performance and power walls due to technology scaling slowdown. Current microprocessors' inability to sustain the historically observed performance scaling has resulted in finding alternatives to improve the target application's execution efficiency. Domain-specific architectures that efficiently utilize hardware acceleration to improve the target application's execution are a good fit for edge computing. As such, we present a domain-specific architecture for an electrocardiogram-based biometric authentication application that improves the performance and energy, compared to the baseline processor, and mitigates timing-based side-channel attack vulnerabilities. The major obstacle in designing domain-specific architectures is that we need to modify application codes to access the accelerators. To address this issue, we propose a programmer-agnostic LLVM-based methodology for generating domain-specific accelerators. Our methodology identifies and ranks the recurrent and similar code blocks within a set of applications that would benefit the most from hardware acceleration, and then integrates the corresponding accelerators into the system to generate domain-specific architectures. Using the methodology, we present a performance and energy-efficient domain-specific architecture for the IoMT applications
