Current distribution simulation results are presented for the metallizaton of 200-mm resistive wafer substrates. A novel horizontal plating cell design that features an insulating hole and a wafer holder that is capable of varying the wafer position vertically during the metallization process is considered to improve the current distribution across the wafer substrate surface. Numerical analysis is used to investigate the influence of the insulating hole size, wafer position, and wafer movement during the deposition process on the current distribution and is compared to experimental data for copper deposition when possible. Submicrometer scale multilevel metallization is one of the key technologies for the next generation of ultralarge-scale integration
