TELFOR 2006

Abstract

Abstract In this paper we propose a scheme for the design of a Symmetrical Multiple Valued Logic (SMVL) arithmetic circuit based on the use of restricted moduli Symmetrical Signed digit Residue Number system (SSRNS). Sign and overflow detection as well as magnitude comparison operations are accomplished without recourse to the traditional complex Mixed Radix number System (MRS) conversion process and multiplicative inverse computation. The method is particularly general purpose systems oriented. Addition operations are executed economically, fast and at constant speed