Lateral DMOS power devices can achieve high breakdown voltage by optimizing the two dimensional (2D) device parameters in accordance with the RESURF principle. However, in practice, it is also necessary to optimize the three dimensional (3D) device parameters in order to support a given breakdown voltage. In this paper, We report the effect of 3D parameters such as the curvatures of the drain and source regions, doping density of LDMOS device with SOI ( Silicon-On-Insulator) substrates based on numerical simulations and analytical solutions using cylindrical coordinates with device simulator "MEDICI" and Synopsys 3D simulator Sentaurus 2009.06-SP2 version. We stress the necessary 3D simulation for power device with racetrack, interdigitated layouts etc
