Abstract The performance of nanoscale Field Effect Diodes as a function of the spacer length between two gates is investigated. Our numerical results show that the I on /I off ratio which is a significant parameter in digital application can be varied from 10 1 to 10 4 for S-FED as the spacer length between two gates increases whereas this ratio is approximately constant for M-FED. The high-frequency performance of FEDs is investigated and the cut-off frequency of the intrinsic transistor without parasitic capacitance is calculated. The figures of merit including intrinsic gate delay time and energy-delay product have been studied for the field effect diodes which are interesting candidates for future logic applications. JNS All rights reserve

E Asl-Soleimani

F Raissi

N Manavizadeh

CiteSeerX

 
 
JNS 3 (2013) 411- 414 
 
Effects of the Spacer Length on the High-Frequency Nanoscale Field Effect 
Diode performance 
N. Manavizadeha,*, F. Raissia, E. Asl-Soleimanib 
a Electrical and Computer Engineering Department, K. N. Toosi University of Technology  
b Thin Films and Nanoelectronic Lab. Electrical and Computer Engineering Department, University of Tehran 
Abstract 
The performance of nanoscale Field Effect Diodes as a function of 
the spacer length between two gates is investigated. Our numerical 
results show that the Ion/Ioff ratio which is a significant parameter in 
digital application can be varied from 101 to 104 for S-FED as the 
spacer length between two gates increases whereas this ratio is 
approximately constant for M-FED. The high-frequency 
performance of FEDs is investigated and the cut-off frequency of the 
intrinsic transistor without parasitic capacitance is calculated. The 
figures of merit including intrinsic gate delay time and energy-delay 
product have been studied for the field effect diodes which are 
interesting candidates for future logic applications. 
 
2014 JNS All rights reserved 
Article history: 
Received  7/10/2013 
Accepted  23/12/2013 
Published online  1/3/2014 
Keywords: 
Field Effect Diode  
Nanoscale Transistor 
Intrinsic Gate Delay Time 
Frequency Response 
*Corresponding author:   
E-mail address: 
manavizadeh@eetd.kntu.ac.ir  
Phone: +98 912 1012898 
Fax: +98 21 84062289 
1. Introduction 
   According to the Moore's law, miniaturization of 
Si devices is reaching its limits. However, ultra 
scaled transistors suffer from short channel effects. 
By employing a Field Effect Diode (FED) structure 
one can improve such effects [1]. The performance 
of digital and analog circuits can be improved by 
replacing conventional MOSFETs by FEDs. They 
have many interesting properties and applications 
such as electrostatic discharge (ESD) protection [2-
4] and memory cells application [5, 6]. 
   A FED is similar to a conventional MOS 
transistor with the exception of using two gates 
over the channel region and oppositely doped 
source and drain (see Fig. 1(a)). As the channel 
length shrinks to dimensions less than 100nm, the 
regular FED has a large off-current. To overcome 
this problem, modified FED (M-FED) (Fig. 1(b)) 
and side-contacted FED (S-FED) (Fig. 1(c)) 
structures have been recently proposed [7,8]. In 
these structures, oppositely doped regions called 
reservoirs are introduced to the source and drain 
regions [9]. FEDs have superior properties to SOI-
MOSFETs, since pinch-off, which limits current in 
MOSFETs, does not occur in FEDs . 
412              
 
 
N. Manavizadeh et al./ JNS 3 (2013) 411- 414 
 
   In this paper, the effect of the spacer length 
between two gates on the electrical characteristics 
and frequency response of M-FED and S-FED is 
investigated and also compared. The figures of 
merit including intrinsic gate delay time and 
energy-delay product, which represent the speed 
and switching energy of the device, respectively, 
are studied. 
 
 
Fig. 1. Schematic structures of (a) regular, (b) modified 
and (c) side-contacted FED. 
 
2. Results and discussion  
   The numerical device simulation results are 
obtained from Dessis (ISE-TCAD device 
simulator), which can be used to simulate 
nanoscale devices with an acceptable level of 
approximations. We have solved the Poisson and 
continuity equations to obtain the electrical 
characteristics of the FED, including I-V 
characteristics and carrier concentrations under 
each gate.  
   We studied FEDs with a gate length of 35nm, a 
body thickness of 50nm, and a gate oxide thickness 
of 2nm. The depths of reservoirs and source/drain 
regions are 50 and 25nm, respectively [10], and a 
device width of 1 µm. It is noted that, the 
channel length of the FED structure is defined 
as Lch = 2Lg + Lsp in which Lg is the constant 
gate length. Therefore, as the spacer length is 
decreased, the channel length is decreased too. 
 
0.6 0.7 0.8 0.9 1 1.10
0.1
0.2
0.3
0.4
I D
S [
m
A
]
10-15
10-10
10-5
100
105
VDS [nm]
I D
S 
[
A
]
 
 
Lsp= 25nm
S-FED
M-FED
(a)
Lsp= 5nm
Lsp= 15nm
 
5 10 15 20 2510
1
102
103
104
105
Lsp [nm]
I o
n/
I o
ff
 
 
M-FED
S-FED
(b)
 
Fig. 2. (a) The output characteristics in the on and off 
state and (b) The Ion/Ioff ratio of the S-FED and M-FED 
as a function of Lsp. 
 
   The output characteristics of FED structures as a 
function of the spacer length (Lsp) are compared in 
Fig.2 (a) in the on and off state. As seen in this 
figure, as the gates are located far from each other, 
the on- and off-current will be decreased. In the 
413              
 
 
N. Manavizadeh et al./ JNS 3 (2013) 411- 414 
 
other words, as Lsp increases, the depletion region 
formed under, widens, therefore, the carrier 
injection through this region will be decreased. As 
a result, the Ion/Ioff ratio can vary from 101 to 104 
for S-FED, whereas this ratio is approximately 
constant for M-FED (see Fig.2 (b)). 
   The intrinsic gate delay time with respect to the 
Ion/Ioff ratio can be employed to compare devices 
with different geometrical and material parameters 
[11]. The gate delay time, which characterizes the 
switching response of a transistor, is an important 
metric for digital electronic applications. The gate 
delay time of a transistor is defined as the time 
taken to charge a constant gate capacitance CG to a 
voltage VDD at a constant current Ion: 
 
on
DDG
I
VC
                                                               (1) 
100 101 102 103 104 105
0.1
0.2
0.3
0.4
0.5
Ion/Ioff
G
at
e 
de
la
y 
[p
s]
S-FED
M-FED
5nm
20nm
15nm
10nm
25nm
25nm
20nm
10nm
15nm
5nm
 
Fig. 3. The intrinsic gate delay time as a function of the 
Ion/Ioff ratio for various spacer lengths between gates.  
 
   Fig. 3 compares the gate delay time as a function 
of the Ion/Ioff ratio for nanoscale FEDs with 
different spacer length between gates. The intrinsic 
capacitance (CG) is calculated from simulation 
results, by the derivation of the total charge present 
in the channel with respect to VGS. The results 
shown in Fig. 3 demonstrate obvious advantages of 
FED devices. The results show that FEDs with the 
spacer length of 5nm have a smaller gate delay 
time in comparison to the other spacer lengths. 
   Fig.4 shows the FEDs gate delay time and EDP 
as a function of the Lsp. As expected, by decreasing 
Lsp, the gate delay time decreases. As shown in 
Fig.4, FEDs have the smallest delay time with 
Lsp=5nm. Fig.4 also illustrates that the minimum 
EDP belongs to S-FED whereas there is no effect 
on the M-FED at various Lsp and this value is 
larger than that of M-FED.  
5 10 15 20 250.1
0.2
0.3
0.4
0.5
G
at
e 
de
la
y 
[p
s]
 
 
0
1
2
3
4
5x 10
-29
Lsp [nm]
En
er
gy
 x
 D
el
ay
 [J
s]
M-FED
S-FED
 
Fig. 4. The intrinsic gate delay time and Comparison of 
the energy-delay product of FEDs as a function of Lsp. 
 
We performed a detailed numerical simulation 
to analyze and optimize the high-frequency 
performance of FEDs. We use the cut-off 
frequency (the frequency at which the current gain 
is 1) to describe the high-frequency of a device. 
The cut-off frequency of the intrinsic transistor 
without parasitic capacitance is  
G
m
T C
g
2
1f

                                               (2) 
where gm and CG are transconductance and gate 
capacitance, respectively. The transconductance, 
gm, is calculated from simulation results by 
414              
 
 
N. Manavizadeh et al./ JNS 3 (2013) 411- 414 
 
5 10 15 20 25
1010
1011
1012
1013
f T
 [H
z/
nm
2 ]
1.5
2
2.5
3
3.5x 10
-4
Lsp [nm]
g m
 [m
ho
]
 
 
M-FED
S-FED
G
DS
m V
I
g


                                                  (3) 
   Fig.5 shows gm as a function of the Lsp for S-FED 
and M-FED. Fig.5 illustrates that by increasing the 
Lsp, the transconductance decreases. As can be 
seen in this figure, by increasing Lsp, the frequency 
response increases. 
 
Fig. 5. The frequency response and transconductance of 
FEDs as a function of Lsp.  
 
3. Conclusion  
   The role of the spacer length between gates on 
the performance of M-FED and S-FED has been 
investigated. Our results indicate that by 
appropriate selection of the spacer length, the 
Ion/Ioff ratio can be increased to 104 for S-FEDs.  
The high-frequency performance of FEDs is 
investigated and the cut-off frequency of the 
intrinsic transistor without parasitic capacitance is 
calculated.  Important figures of merit of FEDs for 
digital applications have been studied. Results 
demonstrate that FEDs can be considered as 
interesting candidates for future digital 
applications. The results reported herein provide a 
facile and with desired properties.  
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Effects of the Spacer Length on the High-Frequency Nanoscale Field Effect Diode performance

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Effects of the Spacer Length on the High-Frequency Nanoscale Field Effect Diode performance

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