Damu Radhakrishnan

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Low Power Arithmetic Units using Pass Logic
Damu Radhakrishnan
Division of Computer Engineering, School of Applied Science
Nanyang Technological University, Nanyang Ave., Singapore 639798
email: asdrkrishnan@ntu.edu.sg
Abstract
There is a tremendous need for miniaturization as well as
low power consumption in many processor architectures,
especially when they are used in portable equipment. In
this context, the design of low power DSP processors
receives utmost importance. A clever means of achieving
this is by use of pass logic circuits in these designs. But
switching activity is found to be a major contributor in
dynamic power consumption. Hence, a formal technique
for calculating the switching activity in CMOS pass
networks is presented in this paper, which is validated
using various designs of CMOS full adder cells. This
technique can therefore be used for the design of CMOS
pass networks, with reduced switching activity, suitable
for use in arithmetic units for the design of smaller and
energy-efficient DSP processors.
1. Introduction
With the fast improvements in technology, the cost of
special purpose processors capable of performing DSP
tasks has dropped significantly to the point where such a
processor can be used in consumer products and other
cost-sensitive systems. As a result, more and more
products have begun using DSP processors, fueling
demand for faster, smaller, cheaper and more energy-
efficient chips. These chips open the door for a new wave
of products to implement signal-processing capabilities.
One of the most popular arithmetic operation in DSP
is multiply-accumulate (MAC). The first major
architectural modification that distinguished DSP
processors from early general-purpose processors was the
addition of specialized hardware that enabled single cycle
multiplication. The design of energy-efficient DSP chips
must therefore be viewed with ways of reducing the
power dissipation of the MAC hardware, especially its
dynamic power dissipation. The dynamic power is caused
by the switching activity of the circuit. The most
significant source of dynamic power dissipation is due to
the charging and discharging of internal parasitic
capacitances in transistors and interconnect capacitances
in integrated circuits [1,3]. The only way to reduce this
power is by analyzing and optimizing various circuit
topologies, which is by itself quite a complex problem to
deal with. When individual logic gates are available
which consume minimum power, they have to be
interconnected to perform the given logical function in
such a way as to obtain the smallest possible number of
switchings for particular gates.  The number of logic gate
switchings is directly related to the consumed power.
Therefore, by way of making the logical synthesis of a
circuit with activities of particular gates taken into
account, one can obtain the circuit with better power and
thermal parameters. In this connection, we shall be
interested in the total switching activity AT on the total
circuit power and in the individual gate activity Ai on
even temperature distribution in the circuit.
Recently, pass logic circuits have been identified as a
clever means to reduce power in CMOS designs. Many
combinational and sequential logic networks implemented
with pass logic have been claimed to reduce the Si area
considerably, while reducing the node capacitances to a
minimum, thereby providing much higher performance
per unit area. Even though many excellent circuits using
pass logic have been reported in the literature, their
switching activities in relation to power have not been
studied so far. Hence in this paper we give an analytical
technique for calculating the switching activity in a
CMOS pass network. Various designs of pass logic adder
cells have been analysed using this technique and are
found to exhibit very good correlation between power and
switching activity.
2. Pass networks
Detailed analysis and synthesis procedures for pass
networks are presented in  [4-7]. A pass transistor is an
nMOS/pMOS transistor with the signal input fed to the
source and the signal output taken from drain. A pass
network is an interconnection of a number of pass
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transistors to achieve a particular switching function.  The
propagation of the signal through the transistor is
controlled by a signal applied to its gate. In the case of an
nMOS transistor, a logic ‘1’ at the gate passes the input
from source to drain and a logic ‘0’ opens the source to
drain path. A pMOS transistor exhibits similar behaviour
with a control signal of logic level 0. If signals 
−
XX  and
Y are connected to the gate and source of an
nMOS/pMOS transistor respectively, then it is denoted as
X(Y) and read as ‘X passing Y’. The variable 
−
XX  is
called a control  variable and Y is called a pass variable.
When both an nMOS and a pMOS transistor are
connected in parallel to pass the signal Y, the circuit is
referred to as a CMOS transmission gate. The logic
symbols and the pass logic expressions for the above
three types of pass gates are shown in Figure 1 [6]. To
avoid any confusion, the same pass logic expression is
used to represent both nMOS and pMOS networks, but
the control signals applied to the gates of the pMOS
transistors are inverted during implementation.
A series connection of a number of nMOS /pMOS
transistors passes the input to the output when all control
signals are high/low. This is represented by the expression
X1X2…Xn(V), where X1, X2,…,Xn are the control
variables applied to the gates of the nMOS transistors
(
−−−
nXXX ,...,, 21  are the control variables applied to the
gates of the pMOS transistors) and V is the pass variable.
A product term P = X1X2…Xn passing an input signal V,
is defined as the pass implicant and is denoted by P(V).
A pass function is formed by the logical sum of a number
of pass implicants and is given by ∑= =
n
1i ii )V(Pf . In a
minimal pass function, all pass implicants belong to the
set of pass prime implicants.
In the pass logic expression, whenever the pass
variable in a pass implicant is a 0/1, a purely
nMOS/pMOS transistor chain can pass it to the output
without any signal degradation. But when a variable is
passed (other than 0 or 1) each individual transistor is
replaced by a transmission gate, but at the expense of
additional inverters for complementing each control
variable.
3.   Switching activity in pass networks
The switching activity for a logic gate refers to the total
number of 0 to 1 and 1 to 0 transitions occurring at the
output of the gate while all possible two pattern input
sequences are applied at the input of the gate. The
switching activity for combinational circuits realized
using gate logic is presented in [2]. The total switching
activity for a complete circuit is equal to the sum of the
switching activities at the individual nodes of the circuit.
To calculate the switching activity, two sets F and R are
used. F is a set with minterms corresponding to the 1's of
the function, and R is a set corresponding to the 0's of the
function. The number of switchings for any gate is given
as a doubled product of the power of these two sets that
are referenced to the output of the gate. If we assume that
0 to 1 and 1 to 0 transitions at a node are equivalent, then
the total switching activity for a logic circuit is given by:
∑=∑=
i
ii
i
iT R.F2AA , where Ai corresponds to the
switching activity at the ith node, and iF and iR
corresponds to the cardinality of the sets Fi and Ri
respectively.
The switching activity for pass networks can be
defined in a manner exactly similar to gate networks. For
a combinational pass network the total switching activity
is equal to the sum of the switching activities at the
individual nodes of the circuit. But the calculation of
switching activity for pass networks is not as direct as in
gate networks. This is due to the inherent nature of pass
networks in which the voltage level at an intermediate
node may also be dictated by the voltage level at the
output node. Thus to find the logic level at each internal
node, both the forward path from the input node as well as
the feedback path from the output node to the node in
question must be considered [8]. But while calculating the
switching activity, the type of network considered
(nMOS, pMOS or CMOS) is immaterial. Hence the
switching activity for a pass network remains the same for
all possible choices of transistors used in the network as
long as the structural pattern is maintained the same for
all the circuits.
Now consider a non-redundant, r variable pass
network as shown in Figure 2 with the pass function given
as: ∑= =
n
1i ii )V(Pf . For this network all the internal nodes
are formed by exactly two branches (two transistors)
connected to each other. But in certain cases, the pass
function given above can be factored further to reduce the
number of transistors in its implementation. When this
happens, some of the internal nodes in the pass network
may have more than two transistors connected to each
other. These cases are shown in Figures 3(a) and 3(b). In
the following the calculation of switching activity at a
node x within the path represented by the pass implicant
Figure 1.  Pass transistor symbols for X(Y)
nMOS transistor
X
Y Y
−
X
pMOS transistor
Y
X
Transmission
       gate
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)V(P ii for the three cases shown in Figures 2, 3(a) and
3(b) are treated differently.
By inspection of the network in Figure 2 let there be k
control variables in forming the product term iP , and m
control variables involved in connecting the variable iV to
node x in the forward path. Obviously, m ≤  k ≤ r. When
m = k, node x becomes the output node f. Let ixP denote
the product term such that ix VV =  when ixP = 1, where
xV denotes the logic level at node x. Also, let xfP denote
the product term such that f = xV  when xfP  = 1. Obviously
iP = ixP xfP . The set F corresponding to node x can now
be generated using Procedure 1 as follows:
Procedure 1:
1) Initialize F = φ  ( the null set ).
2) If 0Vi ≠ , include the product term ixP iV  in F.
3) Find all product terms jP for values of j from 1 to
n, but j ≠ i and 0Vj ≠  such that f = 1 for all such
jjVP while xfP =1. Include all such product terms
xfjj PVP in F.
4) Expand all implicants in F to their minterm
values.
Procedure 2 generates the set R in a similar manner.
Procedure 2:
1) Initialize R = φ  ( the null set )
2) If 1Vi ≠ , include the product term ixP
−
iV  in R.
3) Find all product terms jP for values of j from 1 to
n, but j ≠ i and 1Vj ≠  such that f = 1 for all such
jjVP when 0Vj ≠ , or f = 0 when 0Vj = , while
xfP = 1. Include all such product terms
xfjj PVP
−
in R.
4) Expand all implicants in R to their minterm
values.
In Figure 3(a), the product term forming the network path
connecting the input node iV  to x is  ixP and those
connecting x to output node f are f1xP , f2xP ,…, and
fmx
P . In this case to generate the set F, Step 3 of
Procedure 1 has to be modified as follows:
Modified Step 3 (Procedure 1): Find all product terms
jP for values of j from 1 to n, but j ≠  i and 0Vj ≠  such
that f  = 1 for all jjVP corresponding to each fkxP = 1 for k
= 1,2,…,m. Include all such product terms fkxjj PVP in F.
Similarly, to generate the set R, modify Step 3 of
Procedure 2 as follows:
Modified Step 3 (Procedure 2): Find all product terms
jP for values of j from 1 to n, but j ≠ i  and 1Vj ≠  such
that f = 1 for all such jjVP  when 0Vj ≠ , or f = 0 when
0Vj = , corresponding to each fkxP = 1 for k = 1 to m.
Include all such product terms fkxjj PVP
−
in R.
In Figure 3(b), the product terms forming the network
paths connecting the input node iV (a set of m nodes
im2ii1 V,...,V,V ) to x are x1P , x2P ,…, xmP    and that
connecting x to output node f is  xfP . In this case to
generate the set F, Step 2 of Procedure 1 has to be
modified as follows:
Modified Step 2 (Procedure 1): For every 0Vik ≠ ,
include all product terms ikxkVP in F, for all values of k
from 1 to m. Finally to generate the set R, Step 2 of
Procedure 2 has to be modified as:
Modified Step 2 (Procedure 2): For every 1Vik ≠ , include
all product terms 
−
ikxk VP in R, for all values of k from 1 to
m.
It may be noted at this point that, contrary to the gate
networks,  the sum of the elements in the two sets F and R
may not always add up to 2m for the pass network, where
m denotes the number of variables in the switching
f
V1
P1
Vi
Figure 2. An r-variable irredundant
                pass network
Vn
Pix Pxfx
Pn
Figure 3. An r-variable irredundant factored
                pass network
f
V1
P1
Vi1
Vn
PxfxPx2
Px1
Pxm
Pn
Vi2
Vim
(b)
f
V1
Vi
Vn
Pix
P1
x f2xP
f1x
P
fmx
P
Pn
(a)
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function.
4. Pass logic full adder cells
A structured approach for designing low power adder
cells were presented in [9]. This is done by  partitioning
the  full adder cell into three independent submodules as
shown in Figure 4.
The sum and carry expressions are given by: inCHS ⊕=
and inout HCAHC +=
−
, where BAH ⊕= . Six independent
designs for Module 1 (XOR, XNOR combination), four
for Module 2 and one for Module 3 were given in [9].
They are reproduced here in Figures 5, 6 and 7
respectively using our transistor symbols given earlier. A
total of 25 different choices of adders (including the
conventional CMOS adder) by taking all possible
combinations of the above were simulated and tabulated
in the order of their normalized average power
consumption.
Table 1. Switching activity for 1-bit full adder
Cells sorted by normalized average power
# Cell Avg.
Power
Norm.
Switching
Activity
1 DB 1.00 160
2 DA 1.03 176
3 DD 1.08 176
4 CA 1.14 160
5 BA 1.15 176
6 CB 1.2 144
7 EA 1.22 176
8 CD 1.25 160
9 EB 1.27 160
10 BB 1.27 160
11 BD 1.31 176
12 ED 1.31 176
13 DC 1.35 192
14 FA 1.41 208
15 AA 1.41 208
16 CC 1.46 176
17 FB 1.49 192
18 FD 1.52 208
19 AD 1.53 208
20 EC 1.56 192
21 CMOS 1.56 224
22 BC 1.57 198
23 AB 1.58 198
24 FC 1.71 224
25 AC 1.79 224
Module 1
Module 2
Module 3
H
−
H
A
B
Cin
S
Cout
Full Adder
Figure 4. The building modules of the
                 full adder cell
−
H
Figure 6. Four designs for full adder module 2
SH
−
H
Cin
Cin
Cin
Cin
S
H
Cin
Cin
H
H
0
(a) (b)
H
S
Cin
−
H
Cin
CinH
(c) (d)
0
SH
Cin
Cin
CinH
−
H
A
−
A B −B
−
B
H −
H−
A (a)
A
−
B
−
B
H
B
−
H
(b)
B
−
B
A
A
A
(d)(c)
A
B
0
−
HHB
B
A
A
HB
B
B
A
A
A0
−
HB
B
B
A
A1
A
Figure 5. Six designs for full adder module 1
−
B
−
B
H
B
−
BB
(e)
A
A
A
−
H
B
−
B
B
A
A
A
VDD
H
−
H
B
A
−
A
B
A
−
B
−
A
(f)
−
BB
−
AA
−
B
A
H
Cin
−
H
Figure 7. Design of the full adder module 3
Cout
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The switching activities for all of the above designs
are calculated and are tabulated in Table 1, together with
the power values given in [9]. The different full adder
cells in Table 1 are identified by an ordered 2 letter code,
with the 1st letter representing the cell taken from module
1 (the XOR-XNOR cell) and the second letter
representing the cell taken from module 2 (the XOR cell).
As seen from Table 1, a good match is observed between
switching activity in these cells and the power consumed.
In a few cases the orderings did not match. These can be
accounted for due to the reduced voltage swings occurring
at their internal nodes. Even though this could reduce the
power dissipation at such nodes they do not reflect in the
switching activity of those nodes. Also, the change in
node capacitance at certain nodes was responsible for
modifying the total power dissipation, while not reflecting
on the switching activity.
From Table 1, cell  CB (#6) has the lowest switching
activity of 144 whereas cell DB (#1) has the lowest power
consumption. As can be easily seen the capacitance
effects due to the inverter in design (c) of module 1
increases its power consumption above that of design (d).
Thus cell DB is a better choice as a low power adder cell.
Adder cells constitute a major portion in any large
arithmetic unit. Hence these low power adder cells can be
used to advantage in building large arithmetic units for
minimizing their overall power consumption.
5. Conclusions
Switching activity in CMOS circuits is a good measure of
the overall power dissipation, particularly the dynamic
power dissipation. The calculation of switching activity is
more involved in pass networks as compared to gate
networks because of the feed back paths in pass networks.
In this paper a formal procedure is given to calculate the
switching activity in CMOS pass networks.
The switching activity calculated for various designs
of full adder cells compares well against their power
dissipation, thus justifying its use in CAD tools, for the
analysis and synthesis of CMOS pass logic circuits
suitable for the design of low power arithmetic units.
6.    References
[1] G.M. Blair, “Designing Low Power CMOS”, IEEE
Electronics and Communication Engineering Journal, 1994,
vol. 6, pp. 229-236.
[2] I. Brzozowski and A. Kos, “Minimization of Power
Consumption in Digital Integrated Circuits by Reduction of
Switching Activity”, Proceedings of 25th Euromicro
Conference, Milan, Italy, Sept. 1999, vol. 1, pp. 376-380.
[3] A. Guyot and S. Abou-Samara, “Power Consumption in
Digital Circuits”, Proceedings of 3rd International
Conference on ASIC (ASICON '98), Beijing, China, Oct.
1998.
[4] C. Pedron and A. Stauffer, “Analysis and Synthesis of
Combinational Pass Transistor Circuits”, IEEE
Transactions  on Computer-Aided Design, July 1988, vol.
7, no. 7, pp. 775-786.
[5] D. Radhakrishnan, S.R. Whitaker, and G.K. Maki, “Formal
Design Procedures for Pass Transistor Switching Circuits”,
IEEE Journal of Solid-State Circuits, April 1985, vol. SC-
20, pp. 531-536.
[6] D. Radhakrishnan, “Design of CMOS Circuits”, IEE
Proceedings - Circuits Devices and Systems, Feb. 1991,
vol. 138, no. 1, pp. 83-90.
[7] D. Radhakrishnan, “The Design and Analysis of Pass
Transistor Switching Circuits”, Ph.D. thesis, University of
Idaho, May 1983.
[8] D. Radhakrishnan, “Switching Activity in CMOS Pass
Networks ”, Electronics Letters, Nov. 1999, vol. 35, no. 24,
pp. 2115-2116.
[9] A.M. Shams and M.A. Bayoumi, “A Structured Approach
for Designing Low Power Adders”, Proceedings of 31st
ASILOMAR Conference on Signals, Systems and
Computers, 1998, vol. 1, pp. 757-761.
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Low Power Arithmetic Units using Pass Logic

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Low Power Arithmetic Units using Pass Logic

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