PolySi-SiO 2 -ZrO 2 -SiO 2 -Si Flash Memory Incorporating a Sol-Gel-Derived ZrO 2 Charge Trapping Layer

Abstract

In this paper, we propose a method for depositing the charge trapping layer of a high-k polySi-SiO 2 -ZrO 2 -SiO 2 -Si ͑SOZOS͒ memory device. In this approach, the trapping layer was formed through simple two steps: ͑i͒ spin-coating of the ZrCl 4 precursor and ͑ii͒ rapid thermal annealing for 1 min at 900°C under an oxygen atmosphere. The morphology of the ZrO 2 charge trapping layer was confirmed through X-ray photoemission spectroscopy analysis. The sol-gel-derived layer exhibited improved charge trapping in the SOZOS memory device, resulting in a threshold voltage shift of 2.7 V in the I d -V g curve, P/E ͑program/erase͒ speeds as fast as 0.1 ms, good data retention up to 10 4 s ͑only a 5% charge loss due to deep trapping in the ZrO 2 layer͒, and good endurance ͑no memory window narrowing after 10 5 P/E cycles͒. © 2006 The Electrochemical Society. ͓DOI: 10.1149/1.2337846͔ All rights reserved. The first floating-gate ͑FG͒ nonvolatile semiconductor memory was invented by Sze and Kahng in 1967. 1 Conventional FG memory uses polysilicon as a charge-storage layer surrounded by the dielectric. 2 Although floating-gate structures can achieve high densities and good program/erase ͑P/E͒ speeds and exhibit good reliability in portable flash memory devices, there are concerns regarding the ability to scale up their production. 3 When the tunneling oxide thickness is below 10 nm, the storage charge in the FG leaks readily because defects form in the tunneling oxide after repeated write-erase cycles or through direct tunneling of the current. PolySi-oxide-nitride-oxide-silicon ͑SONOS͒ memory devices have been studied recently as an approach to solving the issue of scaling FG memory. 3 Because of their spatially isolated deep-level traps, SONOS memories exhibit better charge retention than do FG memories that have a bitcell tunneling oxide layer thinner than 10 nm. As a result, a single defect in the tunneling oxide will not cause the discharge of the memory cell. 3 SONOS memory devices use silicon nitride as a charge trapping layer; the conduction band offset between the tunneling oxide and nitride is 1.05 eV. When a positive voltage is applied on the gate, the band bends downward so that the electrons in the Si subconduction band will tunnel through the tunneling oxide and a portion of the nitride will become trapped in the charge trapping layer. Before they become trapped in the nitride, the electrons must tunnel through a portion of the nitride, which degrades the program speed. In addition, because the conduction band offset of the nitride is only 1.05 eV, back tunneling of the trapped electron may also occur. To solve these problems, high-k materials are potential candidates to replace the traditional silicon nitride as the charge trapping layer. The advantages of using high-k materials are the larger band offset with the tunneling oxide and the greater number of trapping sites than those found in silicon nitride. For an HfO 2 high-k material, the conduction band offset between the tunneling oxide and HfO 2 is 1.6 eV. When programming, the electron will tunnel through a shorter distance in HfO 2 than in the nitride to become trapped. This feature can be exploited to achieve high P/E speeds. Thus, it will be beneficial to use a high-k material as the charge trapping layer in a SONOS-type memory device, provided that there are many deep-level trapping sites in the high-k material. Many technologies have been developed recently for the deposition of high-k layers onto tunneling oxides, 7-10 including atomic layer deposition ͑ALD͒, metallorganic chemical vapor deposition ͑MOCVD͒, and physical vapor deposition ͑PVD͒. In the ALD method, ZrCl 4 and H 2 O are used to prepare the ZrO 2 films. For the PVD process, a zirconium metal target is used for sputtering under ambient oxygen to deposit the ZrO 2 films. In the CVD method, ZrCl 4 is used as a precursor to deposit ZrO 2 films. Recently, we proposed the first so-called sol-gel spin-coating method for the deposition of the thin film. 11 Sol-gel spin-coating methods use metal halides hydrolyzed in organic or colloidal solvents to form precursor compounds that undergo hydrolysis, condensation, and polymerization to form metal-oxide networks. The advantages of using sol-gel methods to fabricate high-k films are that they are cheaper than ALD, PVD, and MOCVD approaches, and that various types of thin films can be synthesized. To the best of our knowledge, sol-gel spin-coating of a high-k film has yet to be reported for the preparation of charge trapping layers for flash memory devices. In this paper, we describe the fabrication of a polySi-SiO 2 -ZrO 2 -SiO 2 -Si ͑SOZOS͒ flash memory device prepared through the deposition of ZrCl 4 using the sol-gel spin-coating method and subsequent rapid thermal annealing ͑RTA͒. We performed physical and electrical analyses, including X-ray photoemission spectroscopy ͑XPS͒, I d -V g , retention, and P/E speed measurements, to evaluate the performance of the sol-gel ZrO 2 films for their potential use as charge trapping layers in SOZOS memory devices. Experimental ZrCl 4 ͑99.5%, Aldrich, USA͒ was used as the synthetic precursor of the zirconia. A mother sol solution was first prepared by dissolving ZrCl 4 in isopropanol ͑IPA; Fluka; water content Ͻ0.1%͒ under vigorous stirring in an ice bath. The sol solution was obtained by fully hydrolyzing ZrCl 4 with a stoichiometric quantity of water in IPA to yield a Zr:IPA molar ratio of 1:1000. The fabrication of the sol-gel spin-coated SOZOS memory began with LOCOS isolation process on p-type 150 mm silicon ͑100͒ substrate. At first, a 4 nm tunneling oxide layer was grown thermally at 925°C through furnace oxidation. The Zr:IPA solution ͑molar ratio: 1:1000͒ was coated using a spin-coater at 3000 rpm for 60 s at 25°C. A TEL Clean Track model-MK8 ͑Japan͒ spin-coater was used. The as-deposited thin film was initially baked at 200°C for 10 min to perform densification, followed by high-k RTA for 1 min in an O 2 atmosphere to form the ZrO 2 charge trapping layer. The film thickness, measured using an ellipsometer, was 10 nm. A 30 nm thick blocking oxide was deposited using high-density-plasmaenhanced chemical vapor deposition ͑HDPCVD͒, followed by deposition of a poly-Si gate ͑200 nm͒. After gate deposition, the following processes were applied to fabricate the SOZOS memory: * Electrochemical Society Active Member.