H Iwai

J Song

K Kakushima

K Okamoto

K Tachi

K Tsutsui

M Kouda

N Sugii

P Ahmet

T Hattori

T Kawanago

T Koyanagi

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1
Selection of Rare Earth Silicate
with SrO Capping
for EOT Scaling below 0.5 nm
K. Kakushima, K. Okamoto*, T. Koyanagi*, 
K. Tachi*, M. Kouda*, T. Kawanago*, J. Song*, 
P. Ahmet*, K. Tsutsui, N. Sugii, T. Hattori*, H. Iwai*
Interdisciplinary Graduate School of Science and Engineering, 
*Frontier Research Center
Tokyo Institute of Technology
2
Si
High-k High-k High-k
SiOx interfacial layer (typ.0.5~0.7nm)
Scaling in EOT
limit
excess gate leakage
Continuous scaling in gate dielectrics
SiO2 interfacial layer inserted or re-grown for
- recovery of degraded mobility
- interface state, reliability (TDDB, BTI), etc.
SiO2-IL free structure (direct contact of high-k/Si)
is required for EOT=0.5nm 
Hf based oxide
EOT scaling is expected down to 0.5 nm in ITRS 
0
0.2
0.4
0.6
0.8
1
1.2
2008 2010 2012 2014 2016
ITRS2008
EO
T 
(n
m
)
Year
3
High-k gate dielectrics without SiOx IL
EOT=0.55nmEOT=0.59nm
K. Choi, VLSI symp.(2009)J. Hauang, VLSI symp.(2009)M. Takahashi, IEDM(2007)
EOT=0.49nm
Special process and metal selection 
controlling oxygen atoms against SiOx-IL 
formation
4
1837184018431846
Binding energy (eV)
In
te
ns
ity
 (a
.u
)
300 oC
annealing
Si sub.
La-silicateas depo.
500 oC
annealing
Si substrate
La2O3
La-silicate
W
1 nmSi
k=8~14
k=23
La2O3 + Si + nO2
→ La2SiO5, La2Si2O7, La9.33Si6O26, La10(SiO4)6O3, etc.
La2O3 for gate dielectrics 
La2O3 can achieve a SiOx-IL free structure by 
forming La-silicate at the interface
5
Annealing temperature (oC)
EO
T 
(n
m
)
0.4
0.6
0.8
1
1.2
1.4
0 100 200 300 400 500
La2O3(3nm)
30 min
EO
T 
(n
m
)
Silicate reaction at La2O3/Si interface
Reported La-silicate:
La2SiO5, La10(SiO4)6O3, 
La9.33Si6O26, La2Si2O7, etc.
∆G ~ -100kJ/mol
1. Reactivity with Si substrate
2. Stable silicate phases
LaO1.5:SiO2 from 1:1 to 1:2
Prevent the excess silicate reaction
1. proper metal selection: ECS Trans. 11 (4), 319 (2007)
2. short period annealing: Appl. Phys. Lett. 90, 102908 (2007)
3. other RE-silicates for interfacial layer (this work)
6
Purpose of this work
Selected RE-oxides:
La2O3 (k~23), CeOx (k~32), PrOx (k~32)
1. Material selection of RE-silicate as an 
interfacial layer for SiOx-free gate stack
2. SrO capping effect for further EOT scaling
7
Selection of RE-silicate 
for interfacial layer
8
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
0.0
0.4
0.8
1.2
1.6
2.0
Gate voltage (V)
C
ap
ac
ita
nc
e 
de
ns
ity
 (µ
F/
cm
2 )
EOT=1.4nm
100kHz
CeO2/
Ce-silicate
La2O3/
La-silicate
Pr6O11/
Pr-silicate
Dit=2.6x1011cm-2/eV
Dit=1.6x1012cm-2/eV
Dit=2.5x1012cm-2/eV
C
ap
ac
ita
nc
e 
de
ns
ity
 (µ
F/
cm
2 )
CV curves with La, Ce, Pr-silicates
Low Dit can be obtained with Ce-silicate
500 oC for 30min
nSi
3x1015cm-3
RE-silicate
RE-oxide
W(50nm)
9
1845 1843 1841 1839
Binding energy (eV)
In
te
ns
ity
 (a
.u
.)
La-silicate
Ce-silicate
Pr-silicate
Si sub.
Si-rich
Pr-rich
La-rich
hν =7940eV, Si 1s, TOA=80o
W(8nm)/RE-oxide/RE-silicate/sub.
Si-rich
Ce-rich
XPS measurement of La, Ce, Pr-silicates
Si-rich phase is formed with Ce-silicate
Strong correlation with Dit observed in CV
nSi
3x1015cm-3
RE-silicate
RE-oxide
W(8nm)
hν=7940eV
Synchrotron x-ray
10
~ 6.5~10Pr-silicate
~ 6.1~21Ce-silicate
~ 6.4~9La-silicate
3.2~4.5~32PrOx
3.2~3.7~32CeOx
5.5~24La2O3
Eg (eV)
Dielectric
constantOxide
Material selection for EOT=0.5nm
Combination of La2O3 (Eg=5.5eV) and Ce-silicate 
(k~21) can be a good candidate for scaled gate oxide
Ref: S Sathyamurthy, Nanotech 16 1960 (2005) HJ Osten et al., SSE 47 2161 (2003), 
A. Sakai, APL 85(22) 5322 (2004), O. Seifarth, J Vac Sci Tech B 27 271 (2009)
11
La2O3 with RE-silicate interfacial layer
Fabrication process
HF-last Si wafer
La2O3, CeOx, PrOx depo. (300oC)
La2O3 (1nm) deposition
SrO (1nm) deposition (option)
Sputter tungsten depo. (60nm)
Gate lithography, etching
Annealing at 500oC for 30min 
Si
RE silicate
La2O3
tungsten
La-silicate
Ce-silicate
Pr-silicate
with and w/o SrO
12
0
0.5
1
1.5
EO
T 
(n
m
)
La2O3(1nm) on RE-silicate
La-silicate Ce-silicate Pr-silicate
40% 
down 15% 
down
with SrO capping
w/o SrO capping
500 oC
anneal
for 30min
RE-silicate IL for EOT=0.5 nm
Further EOT reduction can be achieved with 
SrO capping
Interface
layer
50% 
down
13
AR-XPS analysis of SrO/La2O3/CeOx/nSi
(i) Sr 3d/silicate
(iii) La 3d/silicate
(ii) Ce 3d/silicate
20 30 40 50 90
Take-off angle (degree)
In
te
ns
ity
 n
or
m
al
iz
ed
 b
y
ox
id
iz
ed
 S
i i
n 
S
i 2
s
La2O3
La-silicate
Ce-silicate
SrO
Si sub.
Sr atom diffusion to enhance the k-value of La-silicate
analysis without 
metal layer
as deposited, 500 oC annealing
14
NFET characterization
La2O3/Ce-silicate nFET
SrO capped La2O3/Ce-silicate nFET
15
Source/Drain pre-formed Substrate
High-k e-beam evaporation HF-last Si
@ 300oC under ~10-6 Pa
Metal dry etching
SPM, HF-last Treatment
Back side contact formation (Al)
Metal deposition by in situ RF-sputtering
Post Metallization Annealing (PMA)
Contact hole formation
Al wiring for S/D
Al wiring
Al back contact
SiO2S
p-Si
S Dn+ Sn+ Si 2
SiO2S
p-Si
S Dn+ Sn+ Si 2
SiO2S
p-Si
S Dn+ Sn+ Si 2
Metal High-k
NFET fabrication process
16
Output characteristics of nFET
-1.0 -0.5 0.0 0.5 1.0
10-2
10-3
10-4
10-5
10-6
Vg (V)
I ds
(A
)
with SrO
capping
EOT=0.49nm
La2O3/CeSiO
EOT=0.51nm
W/L=20/2.5µm
Vd=50mV
Vd=1V
0.0 0.4 0.6 0.8 1.0
0.8
0.6
0.4
0.2
0.0
Vd (V)
I ds
(m
A
)
W/L=20/2.5µm
0.2
Vg= -0.4, -0.2, 0, 0.2 V
La2O3/CeSiO      with SrO cap
Nice FET operations were confirmed with EOT<0.5nm
SrO capping shifts the Vth from -0.38 to -0.54 V
17
Transconductance of nFET
-1.0 -0.5 0.0 0.5 1.0
0.16
0.12
0.08
0.04
0.00
Vg (V)
g m
(m
S)
with SrO
capping
La2O3
/CeSiO
W/L=20/2.5µm
Vd=50mV
Reduction in gm indicates the degradation in mobility
EOT=
0.51nm
EOT=
0.49nm
18
Effective mobility with SrO capping
Degraded mobility was observed with SrO capping
Possibly due to Sr atoms diffusion down to Si interface
0 0.5 1.0 1.5
150
120
60
30
0
Effective electric field (MV/cm)
E
ffe
ct
iv
e 
m
ob
ili
ty
 (c
m
2 /V
s)
without SrO capping
EOT=0.51nm
90
with SrO capping
EOT=0.49nm
19
Summary of high field µeff on EOT
0.4 0.5 0.6 0.7
250
200
150
100
50
0
EOT (nm)µ
ef
f
@
1 
M
V
/c
m
 (c
m
2/V
s)
Ref [1] Ref [3]
Ref [2]
Ref [4]
La2O3(1.5nm)
/Ce-silicate
La2O3(1.0nm)
/Ce-silicate
SrO
/La2O3(1.0nm)
/Ce-silicate
[1] M. Takahashi, IEDM 523 (2007)
[2] K. Choi, VLSI symp tech 138 (2009)
[3] J. Huang, VLSI symp tech 34 (2009)
[4] A. Ogawa, MEE 84 1861 (2007)
Our data follows the mobility trend in scaled EOT
20
Gate leakage current performance
1.00E-01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
0.3 0.5 0.7 0.9
EOT (nm)
0.5 0.7 0.9
10-1
0.3
10
101
102
103
104
J g
@
 V
g=
1 
V 
(A
/c
m
2 ) ref
Open : w/o SrO capping (1nm)
Close : with SrO capping
SrO(1.5nm)
/La2O3/Ce-silicate 
La2O3(1.5nm)
/Ce-silicate
SrO/La2O3
/Ce-silicate
La2O3/Ce-silicate
SrO/La2O3/Pr-silicate
SrO/La2O3/La-silicate
ITRS 2008 update
J g
@
 V
g=
1 
V 
(A
/c
m
2 )
Measured at Vg=1.0 V
SrO capping can reduce the gate leakage current
21
High-k(La2O3)
metal
Si
Interface rare earth 
silicate (CeSiO)
alkali earth oxide (Sr)
diffusion
High dielectric constant with wide Eg
High diffusion barrier for Sr atoms
Low Dit should be achieved
High k-value and wide Eg
Low fixed charge density by SrO
Suppression of fixed charge generation
Careful process control for diffusion
A proposed guideline for material 
selection in EOT=0.5nm
22
Conclusions
Ce-silicate interfacial layer is suitable for 
scaled gate dielectric
k~20, Eg=6.1 eV, Dit~1011 cm-2/eV
An EOT=0.51 nm can be obtained with by 
the combination of La2O3/Ce-silicate
SrO capping can further reduce the EOT 
at the cost of µeff
A guideline for material selection for EOT 
scaling below 0.5nm is proposed
23
Acknowledgment
This work was supported by NEDO.
The synchrotron radiation experiments were 
performed at the BL47XU in the SPring-8 with 
the approval of the Japan Synchrotron 
Radiation Research Institute (JASRI) (Proposal 
No. 2007A0005). 
24
25
J. Robertson, Solid-State Electronics 49 (2005) 283-293
Ce-silicateLa-silicate
26
TEM image of W/SrO(1nm)/CeOx(1nm)/Si
The presence of Sr atoms are confirmed in Ce-silicate layer
0
0
.0
0
1
0
.0
0
2
0
.0
0
3
0
.0
0
4
0
1
2
3
4
(nm)
Count (a. u.)
Si
Ce
Sr
2nm
W
Si


Selection of Rare Earth Silicate with SrO Capping for EOT Scaling below 0.5 nm

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Selection of Rare Earth Silicate with SrO Capping for EOT Scaling below 0.5 nm

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