This paper presents a hardware implementation of design rule checker using a specialized Content Addressable Memory(CAM) for the Manhattan geometric designs. Two dimensional relationships between rectangular objects in a design are checked with one dimensional design rules. The input data is processed by the pixel pre-processor in such a way that direct comparison between the input data and the stored rules in the CAM is possible. The comparison by the CAM reduces the number of memory references and logic operations of pattern matching and the simple architecture of the system enables a low cost implementation

Ramalingam Sridhar

Seokjin Kim

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VLSI DESIGN
1996, Vol. 4, No. 2, pp. 141-147
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Hardware Design Rule Checker Using a CAM
Architecture
SEOKJIN KIM and RAMALINGAM SRIDHAR*
Department of Electrical and Computer Engineering, The State Universi of New York at Buffalo, Buffalo, NY 14260
This paper presents a hardware implementation of design rule checker using a specialized
Content Addressable Memory(CAM) for the Manhattan geometric designs. Two dimensional
relationships between rectangular objects in a design are checked with one dimensional
design rules. The input data is processed by the pixel pre-processor in such a way that direct
comparison between the input data and the stored rules in the CAM is possible. The com-
parison by the CAM reduces the number of memory references and logic operations of
pattern matching and the simple architecture of the system enables a low cost implementa-
tion.
Keywords: Design rule check, Hardware accelerator, Content Addressable memory.
INTRODUCTION
Special purpose hardware for electrical CAD has
been studied for a number of years. Several experi-
mental systems reported their gain over the general
purpose hardware [1]. As the designs get larger, the
CAD algorithms require more computing and data
processing power and hence the opportunities for a
hardware oriented solutions are increased. To prevent
the drastic increase in the processing time, hierarchi-
cal or online design rule checking methods are often
used during various design phases. However, in prac-
tice, there still exists the need for batch type design
rule checking of the full design for the final verifica-
tion. An efficient hardware implementation of the de-
sign rule check is valuable at this stage.
The mask layout of a design is represented as a set
of images with multiple layers and can be visualized
with bitmap data. The bitmap representation has sev-
eral advantages in hardware implementation. It pre-
serves the geometric shape and the location of an
object and thus it does not need additional steps for
conversion or modification of raw data, which gives
inherent simplicity to the algorithm. The DRC algo-
rithms which use raster scan on bitmap data method,
utilizes a moving window of a certain size which
scans the design onto a fine square grid. The combi-
natorial increase in the table size of the error tem-
plates, as the window size increases, has been a major
limitation of the algorithms for practical applications.
The existing hardware implementations often use a
small size of window, typically 3 3 or 4 4 which
*Corresponding author. 135 Bell Hall, Department of Electrical and Computer Engineering, The State University of New York at Buffalo,
Buffalo, NY 14260 Phone: (716) 645-2422 x2139 Fax: (716) 645-3656 E-Mail: rsridhar@eng.buffalo.edu
141
142 S. KIM and R. SRIDHAR
is not enough to accommodate a practical design rule
and require two dimensional error templates [2][3]. A
variable sized window approach was proposed, how-
ever the implementation is more complex than fixed
size approaches [4]. Others use parallel processing
technique, using a number of small pixel processing
elements connected to each other [5]. Each input
pixel maps directly onto the individual processing el-
ement, which performs simple logic operations with
its neighbors. Even the simple processors need con-
siderable amount of circuitry to perform logic opera-
tions and interactions among the neighbors. The lim-
itation on the window size and the high cost of com-
plex hardware are the factors which make the
hardware implementation of the design rule check
less attractive.
This paper presents a simple and thus a low cost
hardware implementation based on the raster scan
method for the designs in Manhattan geometry. The
system uses a window whose size is big enough to
hold the maximum constraint size in a design rule set.
The window detects corners on a mask layout and
repeats the one dimensional checking along these
corners. This eliminates the need for two dimensional
rule set table at the cost of multiple one dimensional
checkings. The use of one dimensional templates
avoids the drastic increase in the table size and thus
relatively big window can be used. The system con-
sists of a rule set table and a pixel pre-processor. The
rule set table uses a specialized CAM to reduce the
number of memory reference and to eliminate exter-
nal logical comparisons. The pixel pre-processor is a
two dimensional mesh of registers with surrounding
logics and holds the pixel data underneath the win-
dow. The detailed structure and operations are ex-
plained in Sections 2 and 3.
2 CAM BASED DESIGN RULE CHECK
In the bitmap representation of the mask design data,
each pixel has several bits, one corresponding to each
mask layer. A value of 1 or 0 in each bit represents
the existence or absence of the layer on the area cov-
ered by the pixel. The physical size of a pixel is usu-
ally the minimum feature size of a given processing
technology and h is often used as a unit size. Four
basic design rules are width, spacing, enclosure, and
extension rules. These rules use local context of one
or two mask layers at a time. The window based
checkers [2] [3] [4] exploit the locality by having a
moving window which systematically scans through
this bitmap pattern. The size of the window should be
at least unit (h) larger than the size of the maximum
constraint in the rule set. Possible error patterns are
stored in the rule set table. The design rule check is
done by comparing a bitmap pattern under process to
the error patterns stored in the table. The use of con-
ventional memory for the rule set table requires thor-
ough search of the rule table for a matched pattern in
the worst case and thus the memory access path be-
comes the limiting factor for the overall system per-
formance. The Content Addressable Memory(CAM)
has been successfully applied in the pattern matching
or string matching operations where the stored infor-
mation is retrieved based on the data itself, rather
than by its storage location. The input data is com-
pared to each of the memory words in a CAM in
parallel and the result is returned usually in one clock
cycle by a match output, matched data and address-
(es) [6]. Due to the nature of the problem, a CAM
naturally fits the design rule checking. In the pro-
posed method, one dimensional rules are encoded
and stored in a specially designed CAM. The input
pixels from the pixel pre-processing element are
broadcast and compared to the contents of the CAM.
The CAM generates match output with correspond-
ing address in case of any violation or match.
Even though the number of error patterns is finite
for a given window, the combinatorial increase of the
error patterns resulting from the increase of window
size is a significant limitation of this approach [7].
However, considering that a design rule is a distance
between any two objects, it can be expressed in one
dimension even though the checking would be re-
peated in multiple directions or in a circular fashion
with reference to a given pixel. The rule set repre-
sented in one dimension reduces the table size signif-
icantly. A pattern exists for each mask layer. Two of
the layers of interest are scanned from left to right,
DESIGN RULE CHECKER 143
top to bottom one pixel at a time as shown in Figure
3. At the current pixel location, rule checkings are
done in vertical and horizontal directions. Attempts
are also made at the current pixel, vertical and hori-
zontal end of the scan bars and the diagonal counter-
part of the current pixel to detect corners in the pat-
tern. If any of the four attempts detect corners, rule
checkings are done repeatedly at the corners horizon-
tally and vertically up to the size of the maximum
constraint of the given layer. Two pairs of flag regis-
ters (Figure 5) are used to set the maximum con-
straint in each direction. Figure 4 shows an example
of a corner and its checking flow.
3 IMPLEMENTATION
The design rule checker is divided into two func-
tional blocks, the rule set table and the pixel pre-
processor as shown in Figure 5. Each rule in the rule
set is encoded and stored in the CAM with a tag
which holds a code of associated layer(s). A single
word in the CAM represents a rule or constraint. The
pixel pre-processor is used to pre-process incoming
pixels so that direct comparison between the post-
processed pixels and the rules stored in the CAM is
possible.
3.1 CAM for Rule Table
Two mask layers of a design are processed for the
design rule check and thus each pixel holds two bits
of information underneath the pixel in pre-
l/
Minimum spacing 3Z
0 2 10
LdxldolxloiZxolxlllxlxlx]-T[-I I’" .’__1
xl010 ,Ix xlx xl01i.J.... ".i_l__l._
0x01xlx xlxxxl0x 10x01 11 I--
_
Minimum width 4 K
Minimum overlap 2,
Minimum overhang
(a)
FIGURE 2
Io, ,Iolol,loloolxlxlxixlx xl I"" TTI
Io ololololllolllllxlx xl_xx xl /’_’"
Io11I Ioolllololx_xlxl.x_L’ .1:_.._5
(b)
Examples of basic design rules
processing. To store and check the matching of the
information, three bits of the CAM are needed for
pixel information. The design rule encoding scheme
is based on the possible values of a pixel; none, layer
1, layer 2, overlap of layer and 2, and don’t care
Figure 1). Don’t care condition is for those rules
whose constraints are smaller than the size of the
maximum constraint in the rule set. Three bits of the
CAM cell are used to represent 5 logic values, similar
to the method propsed by [8] [9] The don’t care
condition is implemented by setting the most signifi-
cant bit as which sets the match line in the CAM
cell as always high. Several rules and their encoded
results based on the CAM specifications are shown in
Bit’2 Bit1 BitO LOgiC value
0 (white)
0 (layer 1)
0 0 (layer 2)
3 (layer 1.2 overlap)
X (don’t care)
FIGURE 5-valued CAM cell for a pixel
144 S. KIM and R. SRIDHAR
Moving Window with
& horizontal bars
(0,max_Y)
(max_X,0)
Design Database
(max_X,max_Y)
FIGURE 3 Mask scan
Figure 2. The size of a word is fixed to be three times
the size of the maximum constraint in a rule set. The
size of the CAM cell array is determined by the num-
ber of rules in arule set. In our prototype implemen-
tation of the basic MOSIS’s SCMOS rules, the size
of a word is 33 bits as the size of maximum, con-
straint is 10h and the CAM size is chosen to be 64
words. A word in the layer selector has 6 bits which
enables the CAM to have up to 64 logical blocks.
Figure shows the schematic diagram of a single
"pixel bit". The match line is precharged before the
compare operation and the diode-connected N-type
transistor prohibits the connection to the neighboring
bits. If a given input matches with the value stored in
a CAM cell, discharging occurs. If the pixel bit has
the don’t care value, the transistors are turned off
between the precharge line and the discharge path,
and the pixel bit does not affect the comparing oper-
ation at the neighboring bits. Simulation result of
match, mismatch and don’t care conditions are shown
in Figure 9. In the simulation using SPICE3, four bits
are written with values of 0, 1, 2, 3 and tested with
the values under the normal condition and the don’t
care condition.
upflag
Minimum spacing3 dOwn flag
Iol olo IOil Iolol
right flag
\left flag
FIGURE 4 Corner checking procedure
DESIGN RULE CHECKER 145
OUTPUT
J-’ O---UT-_.PU_iBUFFER
J
RULE SET
TABLE
PIXEL ToPIXELOUTPUTcoMPARE
PROCESSIN(3
3
FIGURE 5 System architecture
Since the design rules checking is done for two
layers at a time and the rule set table holds the rules
for all layers, the CAM needs to enable the process-
ing of the corresponding rules to the layers before the
checking operation. The layer relationship to a rule is
stored in the word enable array (Figure 5). If a given
layer information matches one or more words stored
in the layer select array, the corresponding words of
design rule are enabled and ready to compare with
the input data. The detailed circuit diagram of a layer
select word is shown in Figure 6. The memory cells
in the layer select array is the same as that of the
conventional static CAM which performs the exact
match operation. The match sense amplifier senses
and holds the layer match status. The inverted output
of a match sense amplifier enables or disables the
precharge for the subsequent word in the rule set ar-
Layer
Amp
FIGURE 6 Layer select and word enable
ray. The CAM based rule set table is designed using
21a double metal CMOS design rule for fabrication
through MOSIS.
3.2 Pixel Pre-processor
The pixel pre-processor consists of a window buffer,
two pairs of flag registers, four corner detecting cir-
cuits, input and output buffers and a control part. Two
modes of checking are available in the rule checking
operations. A sequential mode checks the pixels in
X-direction and Y-direction of the current reference
pixel sequentially. After the two directional checks,
the window moves by 1 pixel and repeats the checks.
Prior to the horizontal and vertical checks, the diag-
onal checking operation can be activated by detecting
the existence of corner patterns at the four corners of
the window. The corner detectors are designed to de-
tect the conditions of three adjacent pixels at each
corner of the window which determine whether any
of the corner pixels of the window is the corner pixel
of a mask layer. The conditions are similar to that of
corner based DRC algorithms [10]. If a reference
pixel at a corner of the window is in one quadrant and
all three adjacent pixels in the other three quadrants
are of the same type but different from the reference
pixel, the reference pixel is regarded as a corner in a
mask layer. The conditions and schematics of the
northeast corner detector is shown in Figure 7(a) and
7(b) respectively.
If one or more of the four reference pixels are at
the corner, the surrounding pixels within the maxi-
mum constraint of the given mask layer are checked
for violation serially. The serial shifts of the sur-
rounding pixels occur in two directions: horizontal
146 S. KIM and R. SRIDHAR
(a) Cb)
FIGURE 7 Bit locations at Southeast corner and the correspond-
ing corner detector
and vertical. For example, if there is a corner at the
northwest corner of the window, the shift-lefts are
done followed by shift-ups. The circular shift of the
window enables the reference pixel to roll back to its
original position after 22 shift operations in one di-
rection and the shift to another direction can start
with the original pixel data in the frame. The block
diagram of the window buffer and the schematic dia-
gram of a single register are shown in Figure 8(a) and
8(b), respectively. The pixel pre-processor is de-
signed using Xilinx XC3064 FPGA.
4 COMPARISON AND PERFORMANCE
ESTIMATION
The advantages and disadvantages of the proposed
CAM based design rule check are summerized below
as compared to the existing methods.
The use of CAM reduces the number of memory
references and does not require additional hard-
ware for the compare operation.
RIGHT W r-l>
$1 SO CP Reset
FIGURE 8
buffer
(a) (b)
(a) Window buffer (b) single register in the window
The size of the window is large compared to other
window based methods [2][3] enough to hold a
practical design rule and the size of rule table is
not increased drastically since one dimensional
checking is used.
The simple architecture enables a relatively low
cost implementation compared to the variable size
window method [4] and the simple parallel pro-
cessing element method [5].
The sequential corner checking method may de-
grade the performance when a large number of
corners are present in a design.
The performance of the system solely depends on the
speed of the pixel pre-processor if there is no I/O
latency as the CAM performs match operations in
parallel. The number of clocks to process one frame
of window varies according to the number of corners
under the window. If comer is not present, the pre-
processor passes two pixel words in three clock cy-
cles. It takes one clock cycle to detect corner condi-
tions as the four corners of the window are checked
simultaneously. The number of shift operations when
the pre-processor meets a corner is determined by the
maximum constraint size of the layer being pro-
cessed. The total number of clocks to process a win-
dow can be calculated by (1).
N,.to,., 3 + 2c(mc + 1) (1)
where c is the number of corners and mc is the max-
imum constraint size of the layer. Assuming that there
exists one corner in each window and the maximum
(b)
(a) 5-value CAM cell test circuit (b) Simulation result
DESIGN RULE CHECKER 147
constraint size is 10 k, 47 clocks are needed to pro-
cess a window and 1.2 106 k2 of every two layers
can be processed in one minute with 10 MHz clock
speed.
The number of the CAMs required depends on the
number of rules in a rule set. The CAM is designed
with the size of 64 words, and thus a single CAM can
hold upto 64 individual rules. For example, two
CAMs can store the SCMOS design rule provided by
MOSIS which has 118 rules. The multiple use of the
CAMs do not affect the search cycle time, as the
search operation is performed in parallel.
CONCLUSION
This paper has presented a hardware implementation
of bitmap oriented design rule checking. The system
uses a specialized CAM as a design rule set table and
preprocessed input pixel data are compared with the
content of the CAM. The use of CAM reduces the
need for frequent memory accesses, as well as com-
plex template matching which are often required in
the existing systems. A low cost implementation is
made possible by its simple architecture. By repro-
gramming rules in the CAM, the system can be ap-
plied to different process technologies with ease. The
specialized CAM is designed as a custom chip and
the pixel pre-processor is designed on to the XC3064
Xilinx FPGA device.
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Hardware Design Rule Checker Using a CAM Architecture

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