ABSTRACT The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. To further the miniaturization of future products the integration of functions on miniaturized subsystems, i.e. System-inPackage (SiP) is a promising approach. Here, use of recent manufacturing methods allows to merge the SiP concept with a volumetric integration of IC´s. Up to now, most of the systems make use of single-or double-sided populated system carriers. A new challenge is to incorporate not only passive components, but as well active circuitry (IC´s) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to &lt;50µm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB´s. Micro via technology allows to contact the embedded chip to the outer faces of the system circuitry. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. Results on FEM simulations and technical achievements are presented

Alexander Neumann

Dirk Wojakowski

Erik Jung

Herbert Reichl

Rolf Aschenbrenner

CiteSeerX

DownloaProceedings of IMECE 2003, 
November 2003 
THREE DIMENSIONAL PACKAGING OF BARE IC INTO PRINTED CIRCUIT BOARDS FOR SIP 
 
 
Erik Jung, Dirk Wojakowski, Alexander Neumann, 
Rolf Aschenbrenner, Herbert Reichl 
FhG-IZM, TU Berlin 
Gustav-Meyer-Allee 25 
D-13355 Berlin 
erju@izm.fhg.de 
Proceedings of IMECE’03 
2003 ASME International Mechanical Engineering Congress 
Washington, D.C., November 15–21, 2003 
 
 
IMECE2003-41116 
ABSTRACT 
The demand to miniaturize products especially for mobile 
applications and autonomous systems is continuing to drive the 
evolution of electronic products and manufacturing methods. 
To further the miniaturization of future products the integration 
of functions on miniaturized subsystems, i.e. System-in-
Package (SiP) is a promising approach. Here, use of recent 
manufacturing methods allows to merge the SiP concept with a 
volumetric integration of IC´s. Up to now, most of the systems 
make use of single- or double-sided populated system carriers. 
A new challenge is to incorporate not only passive components, 
but as well active circuitry (IC´s) and the necessary thermal 
management. Ultra thin chips (i.e. silicon dies thinned down to 
<50µm total thickness) lend themselves to reach these goals. 
Chips with that thickness can be embedded in the dielectric 
layers of modern laminate PCB´s. Micro via technology allows 
to contact the embedded chip to the outer faces of the system 
circuitry.  
The aspects of embedding and making the electrical 
contact as well as  the thermal management are highlighted. 
Results on FEM simulations and technical achievements are 
presented. 
 
INTRODUCTION 
 
Recent advances in chip thinning allow innovative 
approaches for single- and multichip packaging /1/, thereby 
reducing the required footprint of the package on board. 
Stacking concepts for those packages evolved from stacked 
LCCs via stackable BGA´s towards stackable CSP´s with just 
0.5mm thickness each /1, 2, 3/. The concepts described in these 
references are dedicated to IC packaging, however the 
fundamental technologies developed allow also the direct 
integration of active circuitry into a PCB itself, serving as a 
enabling technology for system in package - SiP. Basically, the 
underlying technology of these approaches described in /1/ and 
/3/ lends itself easily to embedding technologies. Such 
embedding technologies have been investigated and described 
previously /e.g. 4, 5, 6/, lacking the technological advancement 
available today. Thin chips facilitate the use and applicability  
ded From: https://proceedings.asmedigitalcollection.asme.org on 07/02/2019 Terms ofof large area manufacturing techniques commonplace in the 
PCB industry and thereby allow low cost manufacturing of 
SiP´s based on the processes available here. This paper  
presents steps towards this goal and first results are described. 
Technological Issues 
Availability of thin chips 
Three processes are available today to obtain chips with 
remaining silicon thickness less than 100um. All these micro-
thinning approaches rely on a coarse grinding process to 
remove of the wafer about 150um silicon bulk. So far, this 
process is state of the art for mass manufacturing of smart card 
wafers, requiring wafers with no more than 150um thickness. 
At this point, the fragility and stability of the silicon balance 
out. Removing additional material in this coarse fashion 
induces strong stresses and deep in-silicon damages - leading to 
very easy wafer fracture. Micro-Thinning now removes 
additional material and eliminates the stress resulting due to 
micro defects. 
Here, 
 
- Spin Etching /7/ 
- Plasma Etching (ADP Etch, /8/) 
- Grind/CMP /9, 10/ 
 
allow to thin the chips down to less than 50um, even down to 
<10um remaining thickness /11/. The resulting silicon wafer is 
highly flexible and not any more subject to brittle fracture 
Dicing is done a low speed dicing process  with the thinned 
wafer. More recently, laser dicing with or without assisting 
water jet have been successfully demonstrated, showing 
increased dicing speeds /12/. Alternatively, predicing to and 
singulating by the thinning process has been demonstrated 
(Dice-before-Grind, Dice-before-Etch) /13, 14, 15/. In order to 
remain compatible with current PCB manufacturing tolerances, 
at this point the chips must have a rerouting  metallization, that 
enlarge the pitch from typically 80..150um, peripherally, to 
>500um full area array. These (copper) pads can be connected 
to the subsequent layers via following process steps readily 
available in the PCB industry (e.g. chemical deposition, 1 Copyright © 2003 by ASME 
 Use: http://www.asme.org/about-asme/terms-of-use
Downloelectrolytic deposition of metal). With the evolution of the PCB 
manufacturing equipment, it is expected that the pads can be 
clad with e.g. nickel as used for flip chip preparation only, 
foregoing the cost intensive rerouting step. 
Thin Chip Assembly 
For chip assembly to the substrate, the die must be glued to the 
substrate surface with a suitable adhesive and placement 
equipment. The mass manufacturability of thin chip assembly 
has been shown by e.g. Toshiba and Sharp for their multi chip 
stacked CSP /16, 17/. Placement is a very important issue for 
the embedding technique as simultaneous exposure by a mask 
or laser direct imaging is used for the structuring of vias and 
metal routing. Therefore vision systems with top-down 
camera/optics and respective alignment patterns must be 
incorporated into the placement machine to provide a total 
accuracy of ~50µm when using rerouted pads. Smaller 
tolerances will be needed for non-rerouted chips, e.g. 15um. 
Also the die attach adhesive must allow to glue the chip with 
minimal standoff, as too much standoff will prevent successful 
subsequent dielectric coating (Fig. 1). 
 
 
Fig. 1: Thin die with thin (~10um) die attach adhesive 
It was observed, that the thermal mismatch of Si and the PCB 
will result over the curing temperature in a slight bending of the 
composite structure as well as in a copying of the weave and 
waift structure of the embedded glass fibre bundles /Fig. 2 and 
Fig. 3/. 
 
Fig. 2: Warpage due to thermal mismatch 
 
Fig. 3: Weave and Waift copy to chip surface  
aded From: https://proceedings.asmedigitalcollection.asme.org on 07/02/2019 Terms of Lamination 
Covering the mounted IC with the subsequent dielectric layer 
for interconnect and additional routing requires the deposition 
of a suitable material. The use of photosensitive polyimide and 
BCB was successfully shown previously /18/ by spin coating 
technology. As the processing temperatures as well as the 
material compatibility to PCB material (e.g. FR4, FR5, CE etc.) 
is not given, epoxy materials were selected to serve as a 
dielectric. Two approaches were studied - RCC foils as used in 
the micro via manufacturing of PCB which lend themselves 
easily to lamination and laser drilling and spin on coating with 
a PCB compatible epoxy resin. Both processes allow 
temperature budgets well below 200°C. Fig. 4 shows a sample 
with two materials and lamination parameters in a cross 
section. 
With the choice of those influential factors, the slope of the 
cover can be varied between full planarization providing a good 
basis for subsequent layers and a gentle downwards slope 
suitable e.g. for RF applications. Both material and parameter 
sets provide the minimum insulation spacing of 15um as 
required by the target applications. 
 
   
Fig. 4: Effect of Lamination Materials and Process Details on 
the layer geometry – unfilled resin, process parameterset (A), 
filled resin, process parameter set (B) – in (B) the copper has 
been etch stripped for preparation (lamination courtesy AT&S 
and Wuerth Electronic) 
 
Via Formation & Metal Deposition 
In today´s high density PCB manufacturing, laser drilling with 
either excimer lasers or CO2 lasers as well as plasma etching 
/19/ is a well established process for in-dielectric via formation.  
For lamination type of processing, resin clad copper foils were 
laminated to the PCB core with the attached chips. Via holes 
were drilled using a laser drilling tool (e.g. Microline 200 from 
Siemens-Dematic) and a process flow identical to micro via 
manufacturing was targeted. 
Typically, in a PCB manufacturing facility, after via formation 
an electroless Cu seed layer is applied and reinforced by 
electro-deposited 5-15um Cu. While this is an established 
process in the PCB industry using the lamination approach, for 
the laboratory realization an alternative technology according to 
/20/, was chosen with similar results. Electroless contacting the 
via holes requires a clean surface – descum processes are 
therefore state of the art to obtain a surface quality allowing a 
good adhesion of the seed layer /Fig. 5/. 
 
2 Copyright © 2003 by ASME 
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Downloa 
Fig. 5: Thin chip embedded and contacted to via 
Thermal Management 
The assembly of the thin chip to the substrate may be 
accomplished either on the base substrate itself or on a copper 
layer (e.g. large area circuitry) underneath (Fig. 6). The latter 
approach mimicks a built-in heat spreader, that can be attached 
by thermal vias or by heat traps to a larger heat sink. 
If for any reason this approach is not sufficient, active cooling 
by heat pipes or direct liquid cooling has been demonstrated 
previously to be incorporated into the PCB manufacturing 
process /21/. 
Base Substrate
Thin die directly on
base substrate
Thin die on patterned
copper
 
Fig. 6: Different methods for chip attach to the substrate 
Experimental  
For the Ultra Thin Stackable CSP (UT-SCSP), a daisy chain 
interconnect structure of a 10x10mm chip was selected, 
interconnecting the top and bottom side of a commercial PCB 
via the routing traces of the test chip. 
For this proof of concept, the chips had 5um thick electroless 
nickel with a thin copper finish deposited to their aluminium 
pads to allow the contacting with electroless/electrolytic 
processes. This mimicks the copper redistribution layer and 
prevents a phosphorous contamination of the side walls of the 
drilled via hole. The chips were ground to 150um and spin 
etched down to a final thickness of 50µm using a 
carrier/transfer wafer. The assembly and contacting was done in 
the lab scale according to the previous description.  
The drilled and metallized via holes through the PCB (for the 
proof of concept, this was a 10x10cm sized FR4 plate) to route 
the contacts from the top side of the board to the bottom side 
were filled with filler resin to prevent the loss of the dielectric 
material during lamination. This process step was done by the 
PCB manufacturer prior dielectric application. In a standard 
process flow, the holes could also be drilled and metallized 
after layer lamination – eliminating this step. 
Fig. 7 shows a sample view on the contacted chip I/O´s.  
ded From: https://proceedings.asmedigitalcollection.asme.org on 07/02/2019 Terms of U 
Fig. 7: Vias to the Chip I/O´s and routing structures using 
electroless Cu deposition. 
Final capping for solderability and diffusion resistance was 
performed using electroless nickel deposition. 
Fig. 8 shows the cross section of a finished ultra thin stackable 
CSP with solder balls attached at the bottom contact pads. 
 
 
Fig. 8: : Cross section through a UT-SCSP 
 
As seen, the structure will profit from the use of a thinner PCB 
core material, e.g. reducing the core thickness from currently 
0.5 to 0.2mm. shows the a stack of two UT-SCSP assembled in 
simultaneous reflow. 
 
 
Fig. 9: Ultra thin stackable CSP with 0.5mm thickness each 
 
The initial results have yielded a evaluation sample of a PCB 
with embedded thin silicon dice.First characterizations show 
that the samples withstand >1000 cycles of –55/+125°C air/air 
thermal cycling. 
Targeting full PCB manufacturing standards, (half)panels of 
12x18” in size (Fig. 10) were populated with thin dice and 
laminated in a typical PCB process flow.  
 
3 Copyright © 2003 by ASME 
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Downlo 
Fig. 10: Target size of substrate using the lamination process 
 
Fig. 9: Demonstrator of PCB with embedded thin silicon chips 
(lamination: Wuerth Electronic GmbH) 
The lamination of the resin clad copper foil can be tailored to 
ensure a required insulation gap of at least 15µm between the 
conductive structures on the chip and top copper layer. 
Contacting is done by plasma etching (process commercialized 
by Dyconex, CH /19/) and electroless seeding /electroplated 
reinforcement, as described before. Here, the copper on the 
chips serves as an automatic etch stop for the plasma, similar to 
copper of an underlying layer in the original process. 
In order to understand also the impact of die thickness on 
reliability of the assemblies, standard thickness chips were 
laminated into PCB cores using prepreg material instead of 
resin clad copper. Fig. 11 shows the samples obtained. 
Reliability experiments are still running to match the 
experimental data with simulation results. 
 
 
Fig. 11: Embedded thick (500µm) chip in laminate 
 
Testing  
A very critical aspect was testing. Standard electrical PCB tests 
rely on the testing of electrical nets described by the layout  
aded From: https://proceedings.asmedigitalcollection.asme.org on 07/02/2019 Terms of EDA tool. Testers for this check for unwanted connections (e.g. 
shorts) between the nets, or opens in a given net. These testers 
provide a 10V bias either +, or -, either DC or AC. 
Unfortunately, semiconductor devices are quite sensitive to 
reverse voltage and over-voltages and therefore a standard test 
routing cannot be applied to PCB´s with embedded active 
components. A layer-by-layer incircuit test should be employed 
therefore. Alternatively, a full circuit testing after completion of 
the lamination process can be used. As to date, no cost efficient 
repair concept is available, for small number of actives per 
module this might be the cost efficient solution over all. 
 
Future outlook 
On a PCB, optical inserts as demonstrated in /22 / could open 
up a new field for this PCB compatible embedding approach. 
Embedded passive components, liquid cooling and the 
combination with means of advanced packaging like flip chip 
attach or TAB will enable a full system integration into the 
PCB instead of just on the substrate (Fig. 12 and Fig. 13). This 
would grade the PCB up to a higher grade in the value chain, 
minimizing the system designers worry about miniaturization. 
 
 
 
Fig. 12: Application Scenario for  satellite data acquisition 
(courtesy Diehl Electronic) 
 
 
Fig. 13: Vision of a fully integrated system using embedded 
chips, embedded passives, embedded optical waveguides and 
integral cooling /21/ 
ACKNOWLEDGMENTS 
The authors would like to thank ChiP project team as well as 
the colleagues from TUB (3D CSP) having supported this 4 Copyright © 2003 by ASME 
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Downloafeasibility study with activity and discussion. Part of the work 
shown here is done in the BMBF Project "Systemintegration in 
polymere Schaltungsträger", No.02PP2051, co-ordinated by the 
FZK-PFT. The support is gratefully acknowledged. 
REFERENCES 
                                                           
/1/ S. Andersson, "Packaging - Providing Solutions between 
Silicon and System", IEMT 2000, Santa Clara, Oct. 2000, 
Keynote Talk 
/2/ M. Schünemann et al., "MEMS Modular Packaging and 
Interfaces", 50th IEEE Electronic Components and Technology 
Conference, Las Vegas, May 2000 
/3/ Chino et al., "Half-Stacked Milli-CSP", Proc. IEMT 2000, 
Santa Clara, Oct. 2000, pp. 141 
/4/ Eichelberger et al., US Patent US5841193: "Single chip 
modules, repairable multichip modules, and methods of 
fabrication thereof" 
/5/ Hahn et al., „Fabrication of high power MCM by planar 
embedding technique and active cooling“, Micro Systems 
Technology, 1996 
/6/ Klose: „Chip First Systeme und –Gehäuse“, Thesis from 
Univ. Siegen, Germany, Jan. 2000, ISBN 3-8265-6952-0 
/7/ Landesberger et al., Jahresbericht des Fraunhofer-Instituts 
IZM, 1999 
/8/ Savastiouk et al., "3D Wafer Level Packaging" Proc IEMT 
Europe 2000, Munich, April 2000 
/9/ Gaulhofer et al, "Wafer Thinning and Strength Enhancement 
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/10/ PDF-Brochure from http://www.aptekindustries.com 
/11/ Landesberger et al., "Vom starren Wafer zum flexiblen 
Chip", Forum "Dünne Halbleitersubstrate", IZM Munich, Oct. 
2000, Munich 
/12/ “Laser Micromachining Firm Xsil Is Quick to Profits”,  
Semiconductor Innovation, April 2003 
/13/ Juch, "Erfahrungen mit dem Hochratenätzer XPL-900", 
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/14/ Richertzhagen, "Vereinzeln von dünnen Wafern mit dem 
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/15/ electronic article in http://www.semiconductor.net/ 
semiconductor/issues/issues/1999/oct99/docs/assembly.asp 
/16/ Fujitsu et al, "Paper Thin Package", SEMI Japan 
Technology Symposium, Chiba, Dec. 1999 
/17/ Francis, "Thinning Wafers for Flip Chip Applications", 
HDI Magazine, Vol.2 No. 5, May 1999, pp. 18 
/18/Töpper et al., “Flip Chip Interconnection using 
Redistribution Technology”, Advanced Technical Workshop on 
Flip Chip , Brasleton , March 1999 
/19/ for a thorough process description see best information on 
http://www.dyconex.ch 
/20/ Ostmann et al, " Development of an Electroless 
Redistribution Process", Proc. IMAPS Europe 1999, 
Harrowgate, June 1999 
/21/ Public report on the project „Mikrosystemtechnik mit 
flexiblen Schaltungsträgern“, BMFT Projekt 1994, keyword 
"ILFAcool", see also documents available at http://www.ilfa.de  
ded From: https://proceedings.asmedigitalcollection.asme.org on 07/02/2019 Terms of U                                                                                                       
/22/ Detlef Krabe et al , "New Technology for 
Electrical/Optical Systems on Module and Board Level – The 
EOCB Approach ", Proc. 50th ECTC, Las Vegas, May 2000 5 Copyright © 2003 by ASME 
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THREE DIMENSIONAL PACKAGING OF BARE IC INTO PRINTED CIRCUIT BOARDS FOR SIP

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THREE DIMENSIONAL PACKAGING OF BARE IC INTO PRINTED CIRCUIT BOARDS FOR SIP

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