Animesh Datta

Dongkyu Park

Hamid Mahmoodi

Kaushik Roy

Keejong Kim

Saibal Mukhopadhyay

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Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory 
Saibal Mukhopadhyay1, Keejong Kim1, Hamid Mahmoodi2, Animesh Datta1, Dongkyu Park1, and Kaushik Roy1 
1Dept. of ECE, Purdue University, West Lafayette, IN; 2School of Engineering, San Francisco State University, CA 
Email: sm@ecn.purdue.edu; Phone: 765-494-0759; Fax: 765-494-3371 
Abstract- We present a self-repairing SRAM to reduce parametric failures 
using an on-chip leakage sensor and application of proper body bias. 
Simulations in a predictive 70nm technology show 5-40% (depending on inter-
die Vt variation) improvement in SRAM yield. A test-chip is fabricated and 
measured in 0.13µm CMOS to demonstrate operation of the self-repair system.  
Introduction 
Large inter-die and intra-die variations in process parameters 
can result in large number of parametric failures in nanoscaled 
SRAM, thereby, degrading yield [1-2]. In this paper, we present a 
self-repairing SRAM to reduce parametric failures in memory. In the 
proposed technique, a self-repair system detects the inter-die process 
corner of an SRAM die using an on-chip leakage sensor and selects 
the proper body bias to reduce parametric failures. A test-chip is 
implemented in IBM 0.13µm CMOS technology to demonstrate the 
self-repair operation.   
Parametric Failures and Self-Repair of SRAM 
Within-die Vt variation due to random dopant fluctuations 
results in parametric failures (access, read, write and hold failures) in 
SRAM cells [2]. Inter-die shift in Vt can amplify the effect of random 
variation. At low inter-die Vt corners read (lower static noise margin) 
and hold (higher leakage) failures are more probable. At high inter-die 
Vt corners more write and access failures (reduction in the current of 
access transistors) are expected [2] (Fig. 1a, simulations using 
predictive 70nm devices [3]). At nominal Vt corner (region B, Fig, 
1a), low cell failure probability makes memory failure very unlikely 
as most of the faulty cells can be replaced using redundancy. 
However, SRAM dies with negative and positive inter-die Vt shifts 
larger than a certain level are very likely to fail (high memory failure 
probability, Fig. 1a). Reducing read/hold failures in the dies at low-Vt 
corners (region A) and access/write failures in the dies at high-Vt 
corners (region C) can improve yield (shifts the dies from region A 
and C to region B). This can be achieved by applying Forward Body 
Bias (FBB) to high-Vt dies in region C and Reverse Body Bias (RBB) 
to low-Vt dies in region A. Fig. 1b shows that FBB reduces 
access/write failures and RBB reduces read/hold failures [2]. Based on 
above observations, we propose a self-repair technique for SRAM 
(Fig. 2). Inter-die Vt corner of an SRAM die is detected by monitoring 
(using an on-chip leakage sensor) the entire array (composed of a 
large number of cells) leakage and proper body bias is applied to 
reduce failures. The changes in the leakage of individual cells due to 
random within-die Vt variation tend to cancels each other. Hence, 
array leakage is a reliable indicator of the inter-die Vt corner even 
under intra-die Vt variation [2]. The proposed self-repair scheme 
reduces inter-die Vt shift of a die (not intra-die variation) using body 
bias. This greatly decreases dominant types of failure mechanisms in 
that die, resulting in less number of total parametric failures.     
Implementation and Measurements of Test-Chip 
The proposed self-repairing SRAM is implemented in IBM 
0.13µm CMOS (dual-Vt & triple-well) technology (Fig. 2). Two 
64KB SRAMs are implemented to emulate inter-die variations: one 
using low-Vt (representing extreme negative inter-die Vt shift) and the 
other using high-Vt (representing extreme positive inter-die Vt shift) 
devices. The on-chip leakage sensor (current mirror with active load, 
Fig. 3) is designed in series with the cell supply (not with pre-charge 
circuit) to monitor the array leakage. Large and distributed PMOS 
diodes are used in the current mirror to reduce the effect of within-die 
variability (~0.01% area overhead). The sensor output increases with 
array leakage and is compared against on-chip (or off-chip) reference 
voltages (representing low, nominal and high inter-die Vt corners) to 
apply proper body-bias (generated on/off chip). Level converters in 
the body-bias selection circuit (Fig. 4) convert logic “0” to the RBB 
value to prevent conduction through the ‘off’ NMOS transistors of 
pass gates connected to RBB voltage. The pass-gate devices are 
designed with thicker Tox to prevent oxide breakdown when Vg=‘1’ 
and Vs=RBB. The leakage monitors are bypassed (by switching 
“Calibrate” high-to-low) during regular operation using large PMOS 
devices (Fig. 2, ~5% area overhead). Access time is not impacted by 
the bypass PMOS as it is determined by the discharging current 
through access/pull-down NMOS. 
The leakage sensor output (Vout) in the proposed scheme needs 
to have low sensitivity to (a) inter-die Vt shift in the sensor transistors, 
and (b) change in temperature (T). With a diode connected NMOS 
load (Fig. 3a) positive inter-die Vt shift of the diode at the high-Vt 
corner increases Vout. This reduces the difference in Vout between 
low and high-Vt corners (‘Conv. Design’ in Fig. 5). Also, due to 
exponential dependence of array leakage on T, Vout for a high-Vt die 
at high T can be comparable to that of a low-Vt die at low-T (Fig. 5). 
To solve this problem we used active NMOS load with variable bias 
(Fig. 3b). The bias generator circuit is designed such that, the bias 
increases with T and inter-die Vt shift of sensor transistors (with MT1, 
MT2 and MD in Fig. 3b, VBIAS ~ kTln(WT1/WT2) + VtMD). This reduces 
the resistance of the NMOS load at higher T (lower sensitivity of Vout 
to T) and higher inter-die Vt (compensates the Vt increase of NMOS 
load). The transistors M1-M9 are designed to ensure a larger current 
through MT1-MT2-MD at low-Vt corner compared to high-Vt corner. 
This increases VBIAS at a faster rate with T for low-Vt cases to 
compensate the higher temperature sensitivity of array leakage at low-
Vt corner. Simulations in 0.13µm technology show that, the proposed 
sensor reduces the output sensitivity to temperature, inter-die and 
intra-die Vt variation of sensor transistors (Fig. 5). The leakage sensor 
is designed to have Vout~1.4V for low-Vt array and Vout~0V for 
high-Vt array (VDD=1.5V). Measured value of Vout from the sensor 
monitoring the low-Vt array leakage is close to 1.4V (within ~5% of 
the simulated value) (Fig. 3c, array leakage is modified using source-
bias). To represent equal inter-die Vt shift the array and the sensor are 
designed with same types of devices (i.e. the sensor for low-Vt array 
is designed with low-Vt devices). As “Calibrate” switches from 
“high” to “low” during regular operation, the supply of the sensor is 
gated to minimize its static power dissipation. 
The on-chip reference voltages (0.5V and 1V) are designed to 
have a small positive temperature coefficient (similar to Vout, realized 
using NMOS MT1 and MT2) and low sensitivity to inter-die Vt shift 
(Fig. 6). Measured values of the reference voltage show low 
sensitivity to supply variation (Fig. 6c) and to Vt shift (changed using 
body-bias) of the transistors (Fig. 6d). Measured FBB (+0.5V) and 
RBB (-0.5V) values from on-chip bias generators (reference 
generators followed by op-amps [4]) show good stability against 
supply and chip-to-chip variation (Fig. 7). The high-activity row and 
column driver circuits are designed in the isolated p-well to minimize 
body current fluctuation. Moreover, sharp transition at the region 
boundary in Fig. 1a suggests that a small change in Vt can shift a large 
number of dies from region A and C to region B. Also, width of 
region B makes shifting of dies from region A to C very unlikely. This 
suggests that, stability requirement of the generated body bias is not 
very stringent. Measurement results from different chips show that the 
sensor output from low-Vt array is higher than the reference voltages 
(Fig. 8), which indicates that the self-repair system can apply proper 
body bias. Fig. 9 shows the successful transition of body voltage with 
selection of FBB and RBB (measured waveform).   
Measurement of an SRAM cell shows that, FBB increases read 
and write currents which indicate lower access and write failures. 
RBB reduces the read voltage (i.e. voltage rise at node storing “0” 
while reading) which indicates a better read stability (Fig. 10a). 
Simulation in 0.13µm technology shows that the self-repair technique 
can reduce parametric failures at different inter-die corners (Fig. 10b). 
Simulations using 70nm devices [3] shows possibility of significant 
(5-40%, depending on the amount of inter-die Vt variation) 
improvement in design yield (Fig. 10c).  
Conclusions 
We presented a self-repairing SRAM to reduce parametric 
failures in memory. In the proposed scheme global inter-die variation 
is detected and corrected to reduce the effect of local within-die 
random variation. The proposed self-repair technique will help to 
improve SRAM yield under process variation in nanometer nodes. 
 Acknowledgement: This work was supported in part by GSRC, SRC 
(under #1078.001), Intel and IBM Corp. Thanks to MOSIS Educational 
Program for fabrication of the test-chip. 
Reference 
[1] A. Bhavnagarwala, et. al., IEEE JSSC, pp. 658-665, April 2001. 
[2] S. Mukhopadhyay, et. al. ITC, Nov. 2005.  
[3] BPTM: http://www-device.eecs.berkeley.edu/~ptm/ 
[4] K. Itoh, VLSI Memories Chip, Springer, 2001. 
1-4244-0006-6/06/$20.00 (c) 2006 IEEE 2006 Symposium on VLSI Circuits Digest of Technical Papers
Authorized licensed use limited to: San Francisco State Univ. Downloaded on December 10, 2008 at 22:36 from IEEE Xplore.  Restrictions apply.
 
0 10 20 30 40 50 60 70
0.6
0.8
1
1.2
1.4
1.6
1.8
Leakage Current [µA]
S
e
n
s
o
r 
O
u
tp
u
t 
[V
]
Different symbols represent 
data from different chips   
Measurement data from current sensor      
designed using low−Vt devices and 
connected to low−Vt array         
 
 
 
−0.2 −0.1 0 0.1 0.2
10
−10
10
−5
10
0
F
ai
lu
re
 P
ro
b
ab
ili
ty
Inter−die Vt Shift [V]
Hold
Write
Access
Read
Overall cell 
failure 
memory failure 
Region A Region B Region C 
−0.3 −0.2 −0.1 0 0.1 0.2 0.3
0
0.2
0.4
0.6
0.8
1
x 10
−3
F
ai
lu
re
 P
ro
b
ab
ili
ty
Body Bias [V]
Hold
Read
Write    
Access  
Overall Cell        
Failure Probability 
Simulations in predictive 70nm technology 
 
Fig. 1: Effect of (a) inter-die Vt, (b) body bias on SRAM failures; Simulation 
in predictive 70nm technology. 
−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5
−40
−20
0
20
40
60
80
Body bias voltage [V]
%
 c
h
an
g
e 
in
 c
u
rr
en
t/
vo
lt
ag
e
change in 
read voltage  
change in 
read current  change 
in write 
current  
Measurement data from 
an isolated SRAM cell      
Low−Vt Array High−Vt Array
0
1000
2000
3000
4000
5000
6000
T
o
ta
l #
 o
f 
fa
ilu
re
s 
Conv. SRAM
Self−repair SRAM
simulations in 
0.13µm CMOS
(1MB Array) 
0.05 0.1 0.15 0.2
20
30
40
50
60
70
80
90
100
Std. dev of inter−die Vt distribution [V]
Y
ie
ld
 [
%
]
64KB Self−Reparing 
SRAM
256KB 
Self−Reparing 
SRAM     
64KB SRAM 
with ZBB   
256KB SRAM 
with ZBB
 
Fig. 10: Results of self-repair scheme: (a) measurement of single SRAM cell, (b) reduction of parametric 
failures (simulation in 0.13µm), and (c) yield enhancement (simulation in predictive 70nm). 
Bypass
Switch
Online
Leakage
Monitor
Calibrate
Signal
VDD
SRAM
Array
Comparator
Vbody Body-Bias
Generator
Vout VREF1 VREF2
VCO and Decoupling Capacitors
64 KB High-Vt
SRAM
64 KB Low-Vt
SRAM
isocell self repair
circuit
bias
gen
 
Fig. 2: self-repairing SRAM scheme and die-photo. 
   
Fig. 9: Waveform of body voltage transition with body bias selection 
Low reference High reference
0.72 2
0.6 3
40 0.2
M1
MT1
1 0.12
50 0.12
0.7 1
30 0.12
30 0.12
M1
MT1
MT2
MD1
MD2
MT2
0 20 40 60 80 100
0.4
0.6
0.8
1
Temperature (degree C)
R
ef
er
en
ce
 v
ol
ta
ge
 (
V
)
1V reference using HVT
0.5V reference using HVT
1V reference using LVT
0.5V reference using LVT
1.1 1.2 1.3 1.4 1.5 1.6
0
0.5
1
1.5
 Supply Voltage of Reference Ckt [V]
 R
ef
er
en
ce
 V
o
lt
ag
e 
[V
]
High reference voltage  
Low reference voltage  
Measurement data from reference       
circuit designed using low−Vt devices 
and connected to low−Vt array         
Different symbols represent 
data from different chips   
−0.4 −0.2 0 0.2 0.4
0
0.5
1
1.5
Body Bias [V]
R
ef
er
en
ce
 V
o
lt
ag
e 
[V
]
Measurement data from reference       
circuit designed using low−Vt devices
Diff. symbols represent diff. chip’s data   
High reference voltage  
Low reference voltage  
Body−bias is varied to change the Vt of 
the devices: reference voltage show low 
sensitivity to Vt of the devices   
 
Fig. 6: (a) Reference generation circuit, (b) effect of temperature, measured reference voltage with (c) supply (d) body bias variation.   
1.2 1.25 1.3 1.35 1.4 1.45 1.5
−1
−0.5
0
0.5
1
Supply Voltage of Body Bias Gener. Ckt. [V]
B
o
d
y−
b
ia
s 
V
o
lt
ag
e 
[V
]
Forward−bias Voltage  
Reverse−bias Voltage  
Measurement data from 
body−bias generation circuit        
Different symbols represent 
data from different chips   
1 2 3 4 5 6
−1
−0.5
0
0.5
1
1.5
Chip Numbers
B
o
d
y 
B
ia
s 
V
o
lt
ag
e 
[V
]
Measurement data from body−bias
generation circuits from different chips   
Forward body bias voltage  
Reverse body bias voltage  
Fig. 7: Measured body-bias voltage for different chips  
FBB-select RBB-select
Reverse Body voltage 
Forward Body voltage  
FF
FF
VREF2
VREF1
VREF1 > VREF2
VOUT
Calibrate
Body-Bias
Voltage
Level 
Converter
RBIAS
RBB
Level 
Converter
ZBIAS
ZBB
Level 
Converter
FBIAS
FBB
X
X
XB
X
X
XBX
XB
X
 
Fig. 4: Body-bias selection logic
200/0.12
VDD
To SRAM
Array
200/0.12
5/0.12
Vout
200/0.12
VDD
To SRAM
Array
BIAS
Calibrate
200/0.12
5/0.12
2/0.12
Vout
1/0.12
50/0.12
1.4/2.0
30/0.12
1.0/0.12
BIAS
VDD
Calibrate
0.83/0.36
40/0.3
40/0.3
1/0.12
10/0.36
10/0.36
10/0.36
VDD
1/1
Calibrate MT1
MT2
MD
MCM1
M2
M3
M4
M5
M6
M7
M8
M9
 
Fig. 3: Leakage sensor (a) conventional, (b) proposed (c) measured output. 
0 20 40 60 80
0
0.5
1
1.5
2
Temperature [C]
S
en
so
r 
O
u
tp
u
t 
[V
]
Proposed design 
with LVT        
Conv. design with 
diode load in LVT 
Proposed design 
with HVT        
Conv. design with 
diode load in HVT 
simualtion in
0.13µm CMOS
0 0.5 1 1.5
0
10
20
30
40
50
60
70
80
90
Sensor Output [V]
# 
o
f 
o
cc
u
ra
n
ce Proposed 
design   
in HVT   
Conv. design 
with diode   
load in HVT  
Conv. design 
with diode   
load in LVT  
Proposed      
design in LVT 
simulation result in 0.13µm CMOS 
Fig. 5: Leakage sensor o/p with (a) temp. and (b) intra-die variation 
1 2 3 4 5
0
0.5
1
1.5
2
Chip Numbers
R
ef
. a
n
d
 S
en
so
r 
O
u
tp
u
t 
[V
]
Leakage sensor output 
High reference voltage
Low reference voltage
Measurement data from leakge sensor & 
reference circuit (designed with low−Vt 
dev.) connected to the low−Vt array         
 
Fig. 8: Measured sensor o/p & 
reference voltage for diff. chips 
(a) (b)
(a) (b) 
(c) 
(a)
(b) 
(a) (b) (c) (d)
(a)
(b) (c) 
1-4244-0006-6/06/$20.00 (c) 2006 IEEE 2006 Symposium on VLSI Circuits Digest of Technical Papers
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Selfrepairing SRAM for reducing parametric failures in nanoscaled memory

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Selfrepairing SRAM for reducing parametric failures in nanoscaled memory

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