H Ho

T Kwasniewski

V Szwarc

CiteSeerX

 
Design and Implementation of a Multiplierless Reconfigurable 
DFT/DCT Processor 
H. Ho1, V. Szwarc1, and T. Kwasniewski2 
1: Communications Research Centre, 3701 Carling Ave., Ottawa, Ontario, K2H 8S2, Canada 
2: Carleton University, Dept. of Electronics, 1125 Colonel By Drive, Ottawa, Ontario, K1S 5B6, Canada 
 
Abstract  -  A Multiplierless Reconfigurable DFT/DCT 
Processor (MRP) design suitable for multicarrier applications is 
presented. The MRP implementation is based on a 
Reconfigurable Systolic Array (RSA) architecture that supports 
N-point DFT or DCT computations. All multiplication blocks in 
the MRP circuit have been implemented using the CSE-BitSlice 
technique to reduce hardware usage, and power consumption. 
Simulation results show that the MRP DFT circuit 
implementations can be used in most OFDM modulation 
realizations required by broadband communication systems and 
compression schemes of major digital video standards. The 
reconfigurability of the MRP makes it suitable for Shape 
Adaptive DCT (SA-DCT) computations required by object based 
video coding systems.  
I. INTRODUCTION 
 In today’s communications systems, hardware solutions that 
offer computational flexibility are needed to enable the 
systems to operate in a multi-standard and multi-mode 
environment. Furthermore, efficient circuit implementation to 
achieve low hardware usage is essential to many wireless 
applications where cost and power consumption is critical to 
system development. For digital video applications, block-
based DCT is used in the data coding process required by 
many compression standards such as JPEG, MPEG-1 and 
MPEG-2. However, other video standards such as MPEG-4 
require a flexible DCT processor that supports shape adaptive 
DCT (SA-DCT) computations for object-based video coding 
[1-3]. For broadband communications, the DFT technique has 
been widely employed in the modulation/demodulation of 
OFDM subcarriers. A number of reconfigurable FFT 
architectures proposed for OFDM realization in the   802.11, 
DAB, DVB, ADSL and VDSL standards have been published 
in the literature [4-5]. Reconfigurable architectures that 
support both FFT and DCT modes of operation have also been 
proposed for broadband and multimedia applications [6-7]. 
Implementations of DFT and DCT using array multipliers 
result in circuits with high hardware complexity. As a result, 
design techniques that help to minimize or eliminate the use of 
multipliers to achieve circuits with low hardware usage are 
essential for low power broadband and multimedia 
applications.  
In this paper, a circuit that is reconfigurable and supports 
DFT and DCT modes of operation required by different 
OFDM standards and digital video applications is presented. 
The computation of N-point DFTs for OFDM modulation-
demodulation of subcarriers in multiple radio standards such as 
DAB, DVB, VDSL, and ADSL can be carried out by an MRP 
circuit. The MRP can also be configured to compute DCT for 
video compression applications. The MRP has been designed 
and implemented on FPGAs with all multiplication operations 
carried out by building blocks designed using the CSE-BitSlice 
technique [8]. 
II. RSA FOR DFT AND DCT COMPUTATIONS 
In this section, configuration techniques related to 
DFT/DCT implementations on the RSA architecture in order 
to achieve low arithmetic complexity are described [9]. The 
DFT of a finite duration sequence x(n) of length N is 
expressed by the following equation: 
1 2
0
( ) ( )      0,..., 1
N j nk
N
DFT
n
Y k x n e k N
−
−
=
= = −
π
                     (1) 
The DCT of the sequence x(n) is calculated as the real part 
of the DFT of z(n) multiplied by (k) and a twiddle factor 
/ 2
2
k
NW  as follows [10]: 
( )
21
2
2
0
2
2
( ) Re ( ) ( )         0,..., 1
( ) Re ( ) ( )
j nkk N
N
DCT N
n
k
DCT N
Y k k W z n e k N
Y k k W DFT z n
π
α
α
− −
=
= = −
=
          (2) 
where                              
( ) (2 )
   0,..., 1
( 1) (2 1) 2
(0) 1    ;   ( ) 2
z n x n N
n
z N n x n
N k Nα α
=
= −
− − = +
= =
 
If N is a multiple of four, (1) can be rewritten as follows: 
( ) ( )
1 2
1 1
4 4
3 4 3 4
1 1
( ) ( ) ( ) ( )  +
  ( ) ( ) * ( )+  ( ) ( ) * ( )
k
DFT
N N
n n
Y k S n j S n
S n S n a n j S n S n b n
− −
= =
= + −
+ −
                      (3) 
where 
 
( ) ( )
( )
( )
1 2
3
4
3( ) (0) 1 ( ) ; ( ) ( ) 1 ( )
2 4 4
( ) ( ) 1 ( )
2
( ) ( ) 1 ( )
2
2 2( ) cos  ;  ( ) sin
k k
k
k
N N NS n x x S n x x
NS n x N n x n
NS n x n x n
nk nka n b n
N N
π π
= + − = + −
= − + − −
= + − +
= =
 
The output sequences ( )Y N k , ( 2 )Y N k , and ( 2 )Y N k  can 
be inferred to be as follows: 
( ) ( )
1 2
1 1
4 4
3 4 3 4
1 1
( ) ( ) ( ) ( )  +
   ( ) ( ) * ( )   ( ) ( ) * ( )
k
DFT
N N
n n
Y N k S n j S n
S n S n a n j S n S n b n
− −
= =
− = +
+ − −
                    (4) 
( )
( ) ( ) ( )
2
1 2
1 1
4 4
3 4 3 4
1 1
( 2 ) ( ) ( )  
       -1  ( ) ( ) * ( )   ( ) ( ) * ( )
Nk
DFT
N N
n
n n
Y N k S n j S n
S n S n a n j S n S n b n
+
− −
= =
+ = + − +
+ + −
          (5) 
( )
( ) ( ) ( )
2
1 2
1 1
4 4
3 4 3 4
1 1
( 2 ) ( ) ( )  +
       -1  ( ) ( ) * ( )   ( ) ( ) * ( )
Nk
DFT
N N
n
n n
Y N k S n j S n
S n S n a n j S n S n b n
+
− −
= =
− = +
+ − −
          (6) 
As seen from the above equations, by factoring out 
expressions that multiply a common coefficient, a significant 
number of complex multiplications have been eliminated. It 
has also been shown that each set of output sequences 
( ),  ( ),  ( 2 ),DFT DFT DFTY k Y N k Y N k  and  ( 2 )DFTY N k  can be 
calculated simultaneously with N/4 complex multiplication 
operations.  For an N-point DCT, where N is a multiple of 
four, each set of four output sequences ( ),  ( ),DCT DCTY k Y N k−  
( 2 ),DCTY N k+ and ( 2 )DCTY N k− can be calculated simultaneously 
with (N/4)+4 complex multiplication operations. A more 
detailed description of the RSA configurations for DFT 
computations can be found in [9]. 
III. MULTIPLIERLESS RECONFIGURABLE DFT/DCT PROCESSOR 
DESIGN 
A. The MRP Architecture 
In this section, the MRP designs based on the RSA 
architecture depicted in [9] are presented. The MRP design 
consists of an access control block and an RSA building block 
comprised of an 8-by-4 array of processing element (PE) and 
switch (SW) cells as shown in Fig. 1. 
The 8-by-4 RSA building block is the MRP’s computational 
engine for N-point DFTs/DCTs. There are two main building 
blocks in the RSA architecture: the PE and the SW. The PEs in 
the array are interconnected with one another by a network of 
switches. The PE and SW modes of operations are loaded into 
the array under the command of the access control block (AC). 
The DFT/DCT coefficients are also loaded into the PE cells 
based on the addresses generated by the AC block. The 
configuration data and the coefficients can be shifted into the 
array in real time. 
Addr
Conf_Mod
Coefs
X1...N
Y1...N
  RSA
(8-by-4)
 A
cc
e s
s  
C
on
tr
ol
   
   
   
 (A
C
)
X
X ...
1-4
33-36
  X ...
X ...
29-32
61-64
Y1-4 Y5-8 Y13-16
PE PE PE
PE PE PE
SW SW SW
SW SW SW
 
Fig. 1. Architecture of the multiplierless reconfigurable DFT/DCT 
processor. 
This RSA array can be configured to compute a 16-point 
DFT in parallel. The array also supports N-point DFT 
computations for N larger than 16 based on sequential modes 
of operation. The MRP enables 32 input data samples to be 
shifted into the circuit on every clock cycle. Depending on the 
configuration mode, a set of 4 input data samples shifted into 
the PE cell is combined and the result multiplied by the 
factored coefficient. The products generated by the 
multiplication process in the PE cell are then combined with 
partial results shifted in from the PE cell on the north side to 
produce a set of partial results on every clock cycle. For 
sequential mode of operation, the 16 partial results shifted out 
of the RSA block are looped back into the PE cells in the first 
row of the array as shown in Fig. 1. Thus for N equal to 8 or 
16, one clock cycle is needed to shift out a complete set of 
DFT outputs. For N-point DFT computations where N equals 
to 32, 64,…, or 2048, the total number of clock cycles needed 
to shift out N DFT outputs is (N/16)(N/32). For DCT 
computations, one clock cycle is required to compute an N-
point DCT where N is 8 or 16. For N-point DCT computations 
where N is 32, 64,…, or 2048, the total number of clock cycles 
needed to shift out N DCT outputs is (N/16)(N/32)+(N/16). 
The MRP circuit computes the N-point DFT/DCT with a 
latency of N/4 clock cycles.  
For digital video applications where DCT is used in data 
compression algorithms on 8X8 or 16X16 blocks of pixels, the 
8-by-4 RSA can be configured to compute 8-point or 16-point 
1D- DCTs. For 8-point DCT computations, the 8-by-4 RSA 
can perform simultaneously two 8-point DCTs on 2 sets of 
input data, each of which consists of 8 data samples. 
Groupings of two columns of the RSA, in this case, are 
configured to compute 8-point DCTs as shown in Fig. 2. 
The PE consists of multiplier and adder circuits that could 
be configured to implement arithmetic functions that target 
multicarrier applications. The PE can be configured to support 
several modes of operation, including complex multiplication, 
real multiplication, addition or a combination thereof. The 
complex multiplication-accumulation configuration is required 
for DFT implementations while complex multiplication-
accumulation and complex multiplication configurations are 
needed for DCTs.  For DFT implementations, the PE can be 
configured to compute a set of partial results for 
 
( ),  ( ),  ( 2 ),DFT DFT DFTY k Y N k Y N k and  ( 2 )DFTY N k  based on the 
equations described in (3), (4), (5), and (6). 
The SWs in the MRP design route signals from the input of 
the array to the PE cells. The SWs also route the output signals 
of the PE cells to other PE cells as well as to the output of the 
RSA.  
PE Cell
8 -P O I N T  D C T8 -P O I N T  D C T
R S A
XA1-4
XA ...5-8
XB1-4
XB ...5-8
YA1-4 YA5-8 YB1-4 YB5-8  
Fig. 2. Configuration of the 8-by-4 RSA for two 8-point DCT 
computations. 
B. Multiplierless Circuit Design 
In this section, we consider the design of the PE, whose 
multiplier circuits are implemented on the basis of the CSE-
BitSlice technique [8]. The PE consists of four real multipliers 
and twenty real adders that can be configured to perform a 
wide range of arithmetic computations involving the input 
signals and a set of coefficients. The CSE-BitSlice technique 
for multiplication of two variables is used in the design of each 
multiplier. The four multipliers 1 2 3,  ,  ,S S S and 4S in the PE cell 
perform multiplication of the four input data samples 
1 2 3,  ,  ,x x x 4x and four coefficients 1 2 3,  ,  ,C C C and 4C as follows: 
*         1,...,4k kk x C kS ==  
Using the 2-Term decomposition technique, where each 
coefficient component kC consisting of B bits is decomposed 
into two data slices, each of which consists of B/2 digits, the 
real multiplication of kx  and kC  can be expressed as: 
( )
( ) ( ) ( ) ( )
2
2
,2 ,1 , ,2 ,1
, ,1 ,2 , ,1 ,2 ,1 ,2
* * * 2 * *
* * *
2,
B
B
k k k k k k k s k k k
k k s k k k s k k k k k k
S x C x C C x C x C
S x C C x x C C x C C
x xk s k
= = + = +
= • + + • + •
=
 (7)         
     The symbol << represents the shift left operator where 
,1kC and ,2kC
 
are the first B/2 and the last B/2 digits of the 
coefficient component kC  respectively. The symbol    
represents the logical AND operator. By factoring out the 
common digits in  ,1kC   and ,2kC  a total of B/2 additions would 
be required to compute a real multiplication of an input kx  
and the coefficient kC . Thus the total number of additions 
required to compute all four real multiplications using 2-Term 
CSE-BitSlice technique is 2B. Figure 3 depicts the design of a 
multiplier block in the PE cell using the 2-Term CSE-BitSlice 
technique.
 
X 1
X 2
X 3
X 4
X 5 X 6 X 7 X 8
Y 1
Y 2
Y 3
Y 4
C1
C2
R
I
R
I
M
U
X
M
U
X
S k
SE
L
SEL & SHIFT
1
B /2
1
B / 2 - 1
Ck
Xk
Ck2
Common Digit
Identification
CDI
SHIFT&ADD
Ck1
 
Fig. 3. Multiplier block diagram based on the 2-Term CSE-
BitSlice approach. 
IV. MULTIPLIERLESS RECONFIGURABLE DFT/DCT PROCESSOR 
IMPLEMENTATION AND SIMULATION RESULTS 
In this section, FPGA implementation and simulation results 
for the MRP circuit are presented. Two’s complement number 
representation and fixed-point arithmetic has been used 
throughout. Hardware implementations have been carried out 
using Xilinx's 5VLX330FF1760-2 FPGA device. The PE 
circuit implementation is based on the architecture depicted in 
Fig. 3. Complex coefficients consist of 18 bit words with 9 bit 
real and 9 bit quadrature. Each input data bus of the PE cell is 
24 bits wide and each cell output is represented by 34 bits, all 
in complex format. Simulation results for MRP circuit 
implementations based on the CSE-BitSlice technique are 
summarized in Table I. The clock rate performance of the 
MRP shows that the circuit can shift out an N-point DFT every 
22.2 ns for N equal to 8 and 16. The same processing time can 
be achieved for 8 and 16-point DCT computations. For N 
equal to 32, 64,…, 2048, a complete set of N- point DFTs can 
be shifted out after (N/16)(N/32)(1/45) μs based on the MRP 
circuit. Thus, the MRP circuit performance satisfies the 
throughput requirements of several OFDM transmission 
schemes including DAB, ADSL, and the IEEE 802.11a 
standards. Table II shows the performance of the MRP circuit 
configured for various broadband standards in terms of DFT 
size and processing time. It is clear that the MRP circuit 
supports the DFT throughput requirements as it relates to the 
OFDM circuitry for the IEEE 802.11a, DAB, and ADSL 
standards.  Furthermore, the MRP circuit also supports OFDM 
processing throughput requirements of DVB-T and VDSL for 
N up to 2K. The MRP has a flexible architecture, which could 
be used in OFDM transmission schemes where the number of 
subcarriers is not a power of two.  
In multimedia systems where 2D DCTs are used to perform 
data compression on blocks of 8X8 pixels, the MRP can be 
configured to compute DCT on each row and column of the 
8X8 array using a row-column separation strategy [10]. Since 
the MRP can shift out two complete sets of 8-point DCT 
outputs at every clock cycle, a total of 8 clock cycles is 
required to process a block of 8X8 input data. Table III shows 
the performance of the MRP circuit configured for 2D DCT 
 
computations of data frames of different size for various image 
compression standards. 
TABLE I 
IMPLEMENTATION AND SIMULATION RESULTS FOR 
THE MRP CIRCUIT DESIGN. 
Logic Resources/Clock Rate 
FF 32673/207360 (15 %) 
4-Input LUT 122809/207360 (59 %) 
Clock Rate (MHz) 45 
TABLE II 
MRP DFT CONFIGURATIONS AND THROUGHPUT FOR 
DIFFERENT BROADBAND STANDARDS. 
DFT 
(N) 
Standard Transf. Time 
Req. ( s) 
MRP Proc. 
Time ( s) 
64 IEEE 802.11a 3.2 0.18 
256 DAB 31 2.8
512 DAB, ADSL, VDSL 62, 231, 231 11.3 
1024 DAB, VDSL 124, 231 45.4 
2048 DAB, DVB-T, VDSL 248, 224, 231 181 
TABLE III 
MRP DCT CONFIGURATIONS AND THROUGHPUT FOR 
DIFFERENT IMAGE COMPRESSION STANDARDS. 
 
DCT size 
(NXM) 
Standard Proc. Rate Req. 
(Frames/s) 
MRP Proc. Rate 
(Frames/s) 
352X288 SIF 25 3554 
525X720 CCIR-TV 25 953 
1152X1296 HDTV 50 162 
 
From the results in Table III, it can be seen that the MRP 
supports the frame rates required by the Source Input Format 
(SIF) and the International Consulting Committee on Radio 
and Television (CCIR-TV) standard of 25 frames per second. 
The processor throughput performance shows that it also 
supports the required frame rate of the High Definition TV 
(HDTV) standard at 50 frames per second. The MRP circuit 
implementation on the VIRTEX-5 FPGA provides favorable 
frame rate performance for the SIF, CCIR-TV and HDTV 
applications as compared to alternate realizations reported in 
the literature [11]. 
V. CONCLUSION 
A multiplierless reconfigurable DFT/DCT processor suitable 
for broadband and multimedia applications has been presented. 
Simulation results of the MRP circuit configured for DFT and 
DCT computations of various data sizes have shown that the 
MRP satisfies the processing requirements of most broadband 
and digital video standards. Since the RSA is a modular 
architecture, the 8-by-4 RSA building block could be expanded 
to increase the processing power of the MRP circuit. The 
addition of extra rows or columns of PE and SW cells to the 8-
by-4 RSA array would allow the MRP to support the DFT 
transform rates required by the DVB and VDSL standards for 
N equal to 4K and 8K. The MRP can also be configured to 
compute N-point DCTs where N is not a power of two. This 
reconfigurability characteristic enables the MRP to support 
object-based video coding applications where the block of data 
to be processed is of arbitrary geometry. The MRP processor 
has been implemented without the use of conventional 
multipliers and as a result, low hardware usage has been 
achieved. The MRP supports real time reconfigurations of 
DFT, DCT as well as complex multiplication and/or addition 
functions and its flexibility makes it suitable for other 
applications such as software defined radio. 
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Design and Implementation of a Multiplierless Reconfigurable DFT/DCT Processor

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Design and Implementation of a Multiplierless Reconfigurable DFT/DCT Processor

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