Iterative Mode Hardware Implementation of CORDIC Algorithm

Abstract

Abstract This paper presents different hardware implementations of CORDIC (Coordinate Rotation Digital Computer) Introduction The Digital Signal Processing (DSP) has been dominated by low cost microprocessor-based-systems. While these systems offer much flexibility, they are not fast enough for the current DSP applications because yours software algorithms do not meet the demanding Trigonometric functions is one of the mainly tasks performed in DSP applications. Among the existing hardware algorithms for trigonometric solutions the CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the most used. Several works and hardware implementations of CORDIC algorithm are presented and the literature, like This work focuses on a hardware implementation of the Bit-Parallel iterative mode (rotational) CORDIC algorithm with 8, 16 and 32 iterations. To validate this architecture a CORDIC algorithm software implementation was developed. The hardware architectures were implemented in a Spartan3E XC3S500E FPGA and synthesized to X-FAB XC06 standard cells. A comparative study on the performance of these implementations is presented. The paper is organized as follows. Next we introduce the basis of CORDIC algorithm. Section 3 describes the implementation of the serial mode CORDIC in hardware and software. Section 4 provides simulation and synthesis results. Finally, we conclude the paper in Section 5