HARDWARE IMPLEMENTATION OF VIRTUAL RECONFIGURABLE CIRCUIT FOR FAULT TOLERANT EVOLVABLE HARDWARE SYSTEM ON FPGA

Abstract

Abstract This research verify and describes a Virtual Reconfigurable Circuit (VRC) that designed and implemented for a Fault Tolerant Evolvable Hardware (EHW) system used to calculate the thermal power output of Egypt's second Training and Research Reactor (ETRR2) during operation. This circuit have three measured input signals from the reactor core: inlet temperature T in , outlet temperature T out , mass flow rate Q, and one output, which is the calculated thermal power. In any time the true thermal power reading should be available even one input signal get lost due to a problem in its transducer, or wire cutting, …etc. Typically, this is the function of that Fault Tolerant EHW system. The VRC design will implemented over ordinary Field Programmable Gate Array (FPGA) chip. Reducing the FPGA's configuration bits length++ is the main advantage of using VRC. Most VRCs done before used logic based function elements, while in this work, an arithmetic based elements are used, to accommodate the application nature. The design is fully synthesized on ALTERA Cyclone IV GX Family, and the design gave promising results when targeted to the EP4CGX30CF23C6 FPGA chip