Nagpur G H R C O E

Prof P P Rane

Prof S A Nagtode

Snehal Gaikwad

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ISSN 2249-6343 
International Journal of Computer Technology and Electronics Engineering (IJCTEE) 
National Conference on Emerging Trends in Computer Science and Information Technology (NCETSIT-2011) 
(NCETCSIT-2011)  BAPURAO DESHMUKH COLLEGE OF ENGINEERING, SEVAGRAM     Page 15 
 
Sub-degree phase-tuning capability using DDS in 
Digital Down Converter 
 
               Snehal Gaikwad 
1*
                                Prof. P.P.Rane
2
                                Prof. S.A.Nagtode
3 
                          D.M.I.E.T.R, Sawangi (Meghe)                                                         G.H.R.C.O.E., 
Nagpur               
                                 D.M.I.E.T.R, Sawangi (Meghe)
           
                  E-mail-snehal.gaikwad842@gmail.com             E-mail-ashabhandwale@yahoo.com             E-mail-smita_nagtode@rediffmail.com      
 
Abstract- This paper presents the digital architecture of DDS 
eliminates the need for the manual tuning and tweaking related 
to component aging and temperature drift in analog 
synthesizer solutions, The DDC (Digital Down converter) has 
become a cornerstone technology in communication systems. 
Digital down Converter (DDC) is key component of RF systems 
in communications, sensing, and imaging. To extract the band 
of interest at the high sample rate would require a prohibitively 
large filter. Xilinx provides a free DDC core. A DDC consists of 
cascaded integrated comb filter, a mixer and direct digital 
synthesizer (DDS). 
Index Terms- Theory of DDC, Direct Digital Synthesizer 
(DDS), Advantages of DDS, Results 
I. INTRODUCTION 
 
Digital down Converter (DDC) is key component of RF 
systems in communications, sensing, and imaging. Digital 
radio receivers often have fast ADC converters to digitize the 
band limited RF or IF signal generating high data rates; but in 
many cases, the signal of interest represents a small 
proportion of that bandwidth. To extract the band of interest 
at this high sample rate would require a prohibitively large 
filter. A DDC allows the frequency band of interest to be 
moved down the spectrum so the sample rate can be reduced, 
filter requirements and further processing on the signal of 
interest become more easily realizable. A fundamental part of 
many communications systems is Digital Down Conversion 
(DDC). A Digital down Converter is basically complex 
mixer, shifting the frequency band of interest to baseband. 
The DDC is typically used to convert an RF signal down to 
baseband. It does this by digitizing at a high sample rate, and 
then using purely digital techniques to perform the data 
reduction. 
 
A.   Overview of the DDC implementation 
 
High Speed 
ADC
DDC
Additional 
Signal 
ProcessingIncoming RF/IF signal
2 MBytes/s 0.2 MBytes/s
10
 
Figure 1 Overview of the DDC Function 
Consider a signal lying in the range 10-20 KHz.  The signal 
bandwidth is 10 KHz.  However, it is often digitized with a 
sampling rate over 1 M samples per Second, representing in 
the region of 2Mbyte/second. The DDC allows us to select 
the 10-20 KHz band, and to shift its frequency down to base-
band and in doing so reduce the sample rate, with a 10 KHz 
bandwidth, a sample rate of 100 KHz would be fine - giving 
a data rate of only 0.2Mbyte/second.  This is shown in 
Figure 1. 
II.  DDS (DIRECT DIGITAL FREQUENCY 
SYNTHESIZER) 
 
The DDS (DDS synthesizer) is an implementation of a direct 
digital frequency synthesizer (DDS) (also called Number 
Controlled Oscillator, NCO) which produces a sine wave at 
the output with a specified frequency and phase (adjustable 
at run time). The resolution of the Frequency Tuning Word 
(FTW), the phase and the amplitude are defined separately. 
While the FTW resolution can be set by the generic 
ftw_width, phase and amplitude resolution are defined as 
constants phase_width and ampl_width in the separate 
package sine_lut_pkg. This is generated by a Matlab script 
(sine_lut_gen.m), the m-files are described in their headers.  
The nomenclature of the files is  
sine_<phase_width>_x_<amplitude_width>_pkg. hd. By 
adding one of these files to the project, the resolution of 
phase and amplitude is automatically defined. The function 
of the DDS is to generate the frequency equal to the 
sampling frequency of the first stage. The figure 2 shows the 
implementation of the DDS. A direct digital synthesizer 
operates by storing the points of a waveform in digital 
format, and then recalling them to generate the waveform. 
The rate at which the synthesizer completes one waveform 
then determines the frequency 
[1],
 
[2].
 
 
ISSN 2249-6343 
International Journal of Computer Technology and Electronics Engineering (IJCTEE) 
National Conference on Emerging Trends in Computer Science and Information Technology (NCETSIT-2011) 
(NCETCSIT-2011)  BAPURAO DESHMUKH COLLEGE OF ENGINEERING, SEVAGRAM     Page 16 
 
Z-1 Z-1 1/4 
Sine 
LUT
2 M-2 - 1
FTW
N
PTW
Phase
M
N
M
Phase (M-3) ... 0
Phase 
(M-2) Phase 
(M-1)
-
0
1
0
1-
PTW - Phase Tuning Word
FTW - Frequency Tuning Word
Amplitude
 
Figure 2 Direct Digital Frequency Synthesizer 
A. Performance Details of DDS 
 
The frequency and phase of the DDS can be controlled using 
the FTW (Frequency Tuning Word) and PTW (Phase 
Tuning Word).  
The output frequency will be determined by the FTW. 
Fdds = (FTW/2
(N-M)
)*(Fclk / (2
M
)) or 
Fdds = FTW*Fclk/2
N
 
Where Fclk = Clock Frequency 
The initial phase can be controlled by PTW. 
Φdds= (PTW/2
M
)*2*pi 
Match the DDS frequency to the sampling frequency so that 
the spectrum gets shifted towards DC (0 Hz). 
B. Advantages of DDS 
 
Today’s cost-competitive, high-performance, functionally 
integrated DDS ICs are becoming common in both 
communication systems and sensor applications. The 
advantages that make them attractive to design engineers 
include [7]: 
1) Extremely fast hopping speed in tuning output frequency 
(or phase); phase-continuous 
frequency hops with no overshoot/undershoot or analog-
related loop settling-time anomalies, 
2)The digital control interface of the DDS architecture 
facilitates an environment where systems can be remotely 
controlled and optimized with high resolution under 
processor control. Design and FPGA Implementation of 
High Speed, Low Power Digital up Converter for Power 
Line Communication Systems. 
III. RESULTS 
A.  Simulation results for DDS 
Sampling Frequency : 60 MHz 
 
 
 
Table 1: Parameters used for DDS module: 
 
Parameter Parameter Name Data Types Value  Units 
Frequency 
Tuning 
Word 
 
FTW_WIDTH 
 
Integer 
 
11 
 
Bits 
Phase 
Tuning 
 
PHASE_WIDTH 
 
Integer 
 
9 
 
Bits 
Word 
Output 
Amplitude 
Word 
 
AMPL_WIDTH 
 
Integer 
 
16 
 
Bits 
 
 
 
Table 2:  VHDL simulation results are shown below. 
 
 
Frequency 
Required 
 
FTW 
 
FTW 
actual 
 
Frequency 
Generated 
Actual 
Frequency 
from 
Simulatio
n 
 
Results 
 
10MHz 
 
341.33
33 
 
341 
 
9.99MHz 
 
9.978MH
z 
 
Figure 
3 
 
15MHz 
 
512 
 
512 
 
15MHz 
 
15.000M
Hz 
 
Figure 
5 
 
0 10 20 30 40 50 60
-4
-2
0
2
4
x 10
4
0 1 2 3 4 5 6
x 10
4
-400
-300
-200
-100
0
Spectrum of Output
Frequency
A
m
p
lit
u
d
e
 
 
Output Frequency =15000.5 KHz
 
Figure 3 
0 10 20 30 40 50 60
-3
-2
-1
0
1
2
3
x 10
4
0 1 2 3 4 5 6
x 10
4
-100
-80
-60
-40
-20
0
Spectrum of Output
Frequency
A
m
p
lit
u
d
e
 
 
Output Frequency =20022.5 KHz
 
Figure 4 
 
 
ISSN 2249-6343 
International Journal of Computer Technology and Electronics Engineering (IJCTEE) 
National Conference on Emerging Trends in Computer Science and Information Technology (NCETSIT-2011) 
(NCETCSIT-2011)  BAPURAO DESHMUKH COLLEGE OF ENGINEERING, SEVAGRAM     Page 17 
 
IV. CONCLUSION 
This paper deals with the development of a Digital down 
Converter for Communication system equipment. DDC 
performs mixing to shift the signal spectrum from the 
selected carrier frequencies to base-band, decimation to 
reduce the sample rate, and filtering to remove adjacent 
channels and minimize aliasing. Here DDS has digitally 
controlled micro-hertz frequency-tuning and sub-degree 
phase-tuning capability. 
In the course of doing the project, insight knowledge has 
been gained into various fields like 
• The Virtex II Pro FPGA architecture. 
• Coding using Verilog. 
• Digital signal processing concepts. 
• Network and communication concepts. 
• Tools such as Xilinx ISE, ModelSim, and Matlab and 
Xilinx system generator. 
 
 
V. FUTURE WORK 
With a DDC, if the system operates at all, it works perfectly 
– there’s never any tuning or component tolerance to worry 
about. As rate is programmable, then amplitude modulation 
can achieve with DDC in communication system. The 
design of code requires hardware with more resources as it 
exceeds the capacity of lower FPGA devices.  
 
 
REFERENCES 
[1] Xilinx LogiCORE,”Digital Up Converter (DUC) v1.4”, DS276 May 23, 
2005 www.xilinx.com 
[2] Lattice Semiconductor Corporation, “The FPGA as a Flexible and Low-
Cost Digital Solution for Wireless Base Stations”, A Lattice  
Semiconductor White Paper, March 2007 
[3] Matthew P. Donadio, “CIC Filter Introduction”, For Free Publication by 
Iowegian,m.p.donadio@ieee.org, 18 July 2000 
[4] Pavel KOVAR, “Generation of the Narrow Band Digital Modulated 
Signals Using Quadrature Digital Up Converter”, RADIO ENGINEERING, 
VOL. 12, NO. 1, APRIL 2003 
[5]Direct digital synthesis (DDS) http://www.radioelectronics.   
     com/info/receivers/synth_basics/dds.php 
[6] QAN19 Modulating Direct Digital Synthesizer in a quick logic FPGA   
http://www.quicklogic.com/images/appnote19.pdf (Accessed on April 10, 
2006) 
[7] Eva Murphy and Colm Slattery, “All about Direct Digital Synthesis”,  
Analog dialogue 38-08, August 2004,  
 http://www.analog.com/analogdailogue 
[8] Xilinx LogiCORE,”Multiply Accumulator v4.0”, DS336 April 28, 2005 
www.xilinx.com 
[9] Cyril Prasanna Raj P and Subash, “SASTech Journal”, Vol 4. PP 33-39, 
September 2006 
[10] S. Signell, T. G. Kouyoumdjiev, K. H. Mossberg, “Design and 
Analysis of Bilinear Digital Ladder Filters”, IEEE Trans. on Circuits and 
Systems, Vol. 43, No. 2. February 1996. 
 
 
 
 
 
 
 
 
 
 
First Author- Ms.Snehal Gaikwad 
M.Tech (VLSI), Pursuing  
Lecturer, Dept. of Electronics Engg. 
D.M.I.E.T.R., Sawangi (Meghe), Wardha 
Publication -02 
Achievement- SCJP by Sun Microsystems 
 
Second Author- Prof. P.P.Rane 
M.Tech (Electronics) 
Asst. Professor, Dept of Electronics Engg. 
G.H.Raisoni College of Engg, Nagpur 
Publications-02 
 
Third Author- Prof. S.A. Nagtode 
M.E. (Electronics), P.hD (Pursuing) 
Asst. Professor, Dept of E&TC 
D.M.I.E.T.R., Sawangi (Meghe), Wardha 
Publications-05 
 


Sub-degree phase-tuning capability using DDS in Digital Down Converter

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Sub-degree phase-tuning capability using DDS in Digital Down Converter

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